RECOMMENDED TECHNOLOGY PAPERS
Protecting Electronics with Parylene
This whitepaper provides a comprehensive overview of parylene conformal
coating, advantages of parylene, and applications for parylene to
protect electronic devices.
As technology continues to advance, devices will encounter rugged
environments and it is vital that they are properly protected. Parylene
conformal coating is one way that manufacturers are giving their devices
a higher level of protection, along with increasing the overall quality
of their products.
Parylene conformal coating applications for Electronics include:
· I/O & PCI Modules
· Power Converters and Supplies
· Other Embedded Computing applications
· Other specialty electronics and assemblies April 26, 2016
Sponsored by Diamond-MT
NMT: A Novel Technology for In-Line Ultra-Thin Film Measurements
XwinSys identified the semiconductors recent market trends and developed a novel XRF technology, named NMT: Noise-reduced Multilayer Thin-film measurement. This innovative approach can be used for in-line inspection and metrology features, to accurately and precisely analyze single and multi-layered elements in ultra-thin films. NMT novel technology can be utilized for in-line applications ranging from localized ultra-thin film stacks to the inspection of 3D localized features to the analysis of defects involving geometries, voids and material elements. February 23, 2016
Sponsored by XwinSys Technology Development Ltd.
Adhesives for Electronic ApplicationsMore Technology Papers
Master Bond custom formulates epoxy adhesives, sealants, coatings, potting and encapsulation compounds to meet the rigorous needs of the electronic industry. We are a leading manufacturer of conformal coatings, glob tops, flip chip underfills, and die attach for printed circuit boards, semiconductors, microelectronics, and more. Browse our catalog to find out more.January 05, 2016
Sponsored by Master Bond, Inc.,
Advanced Packaging: A Changing Landscape Rife with Opportunities
May 10, 2016 at 1 PM ET / Sponsored by Brewer Science
Die stacking enables better chip performance in a small form factor, meeting the needs of smartphones, tablets, and other advanced devices. Through-silicon vias are moving into volume packaging production, but problems with reliability, cost, and scaling remain. The supply chain also must adjust to this “mid” step between front- and back-end chip production. This webcast will explore the wafer thinning, bonding, TSV formation and other critical process steps necessary to enable 3D integration.
Trends in MEMS
May 11, 2016 at 12 PM ET / Sponsored by Boston Semi Equipment
MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.
Fan-Out Wafer Level Packaging
May 2016 (Date and time TBD) / Sponsored by Zeta Instruments
Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging. Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market. In this webcast, industry experts will explain the FOWLP process, discuss recent advances and forecast future trends.