3D Integration

MAGAZINE



3D INTEGRATION ARTICLES



Surface matters: Huge reduction of heat conduction observed in flat silicon channels

04/23/2015  A paper published in ACS Nano describes how the nanometre-scale topology and the chemical composition of the surface control the thermal conductivity of ultrathin silicon membranes.

Synopsys' modeling of 10nm parasitic variation effects ratified by open-source standards board

04/21/2015  Synopsys, Inc. today announced new extensions to its open-source Interconnect Technology Format (ITF) which enable modeling of complex device and interconnect parasitic effects at the advanced 10-nanometer (nm) process node.

KLA-Tencor introduces new portfolio for advanced semiconductor packaging

04/16/2015  Today, KLA-Tencor Corporation announced two new systems that support advanced semiconductor packaging technologies: CIRCL-AP and ICOS T830.

A*STAR's IME and partners to enable low cost packaging technology for system scaling within smart devices

04/15/2015  A*STAR’s Institute of Microelectronics (IME), together with industry partners, have formed a High-Density Fan-Out Wafer Level Packaging (FOWLP) consortium to extend FOWLP capabilities for applications in devices such as smart phones, tablets, navigation tools and gaming consoles.

ClassOne enters ECD lab partnership with Shanghai Sinyang

04/14/2015  Semiconductor equipment manufacturer ClassOne Technology announced today that it has signed a joint electrochemical deposition (ECD) applications lab agreement with Shanghai Sinyang Semiconductor Materials Co., Ltd.

Duke University research advances testing of 3D integrated circuits for cost-effective development of electronics

04/14/2015  Duke University researchers are working to advance the tools and methodologies used to test 3D integrated circuits (ICs), which promise to help ensure the ongoing development of higher performance, lower power semiconductor chips.

Consider packaging requirements at the beginning, not the end, of the design cycle

04/02/2015  Consider these eight issues where the packaging team should be closely involved with the circuit design team.

MORE 3D-INTEGRATION ARTICLES

HEADLINES

FINANCIALS



TECHNOLOGY PAPERS



ASIC Design Made Cost Effective with Low Cost Tools and Masks

For smaller projects or companies with modest design budgets, ASIC design is becoming a viable option due to low cost design tools and easy access to flexible, mature IC processes. This is especially compelling for developing mixed-signal ASICs for cost-sensitive sensor applications for the Internet of things (IoT). This paper discusses how costs and risks can be reduced using multi-project wafer services, coupled with affordable design tools for developing mixed-signal ASICs. April 13, 2015
Sponsored by Mentor Graphics

High-Performance Analog and RF Circuit Simulation

The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Key challenges in the design of these circuits include block-level characterization and full-circuit verification. This paper highlights these verification challenges by discussing the results of a 2.2 GHz PLL LC-VCO, a 12-bit pipeline ADC, and an ultra-wideband transceiver.March 13, 2015
Sponsored by Mentor Graphics

How to Use Imaging Colorimeters for FPD Automated Visual Inspection

The use of imaging colorimeter systems and analytical software to assess display brightness and color uniformity, contrast, and to identify defects in FPDs is well established. A fundamental difference between imaging colorimetry and traditional machine vision is imaging colorimetry's accuracy in matching human visual perception for light and color uniformity. This white paper describes how imaging colorimetry can be used in a fully-automated testing system to identify and quantify defects in high-speed, high-volume production environments.February 27, 2015
Sponsored by Radiant Vision Systems

More Technology Papers

WEBCASTS



Trends in Materials: The Smartphone Driver

Thursday, April 30, 2015 at 1:00 p.m. EST

To understand 3-D FinFET doping and high mobility channel material, this talk will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET.

Sponsored By:
MEMS

May 2015 (Date and time TBD)

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.

Sponsored By:
Interconnects

June 2015 (Date and time TBD)

This webcast will examine the state-of-the-art in conductors and dielectrics, -- including contacts and Metal1 through global level -- pre-metal dielectrics, associated planarization, necessary etch, strip and cleans, embedded passives, global and intermediate TSVs for 3D, as well as reliability, system, and performance issues.

Sponsored By:
More Webcasts

VIDEOS



EVENTS



ASMC 2015
Saratoga Springs, NY
http://www.semi.org/en/asmc2015
May 03, 2015 - May 06, 2015
The ConFab
Las Vegas, Nevada
http://www.theconfab.com
May 19, 2015 - May 22, 2015
65th Annual ECTC
San Diego, CA
http://www.ectc.net
May 26, 2015 - May 29, 2015
SID Display Week 2015
San Jose, California
http://www.displayweek.org
May 31, 2015 - June 05, 2015
Design Automation Conference (DAC)
San Francisco, CA
https://dac.com
June 07, 2015 - June 11, 2015