3D Integration

3D INTEGRATION ARTICLES



MEMSIC introduces the world's first monolithic and wafer level packaged 3D-axis accelerometer

08/15/2014  MEMSIC, Inc., a MEMS sensing solution provider, announced today the availability of its MXC400xXC, the world's first monolithic 3D accelerometer, and also the first 3D accelerometer to utilize WLP technology.

Si2 announces new director of 3DIC programs

08/14/2014  The Silicon Integration Initiative (Si2), a global semiconductor standards consortium, announced today that Herb Reiter is joining the team of professionals in the role of Director, 3D IC Programs.

Materials matter — Enabling the future of IC fabrication and packaging

07/31/2014  The SEMI Strategic Materials Conference, held September 30–October 1 in Santa Clara, Calif., will examine the drivers for new materials and how they impact material suppliers and the value chain they serve.

Fusion bonding for next-generation 3D-ICs

07/24/2014  Recent developments in wafer bonding technology have demonstrated the ability to achieve improved bond alignment accuracy.

A*STAR and industry partners form S$200M semiconductor R&D joint labs

07/24/2014  Four joint laboratories, representing a commitment of S$200m between private and public sectors, were launched today between A*STAR's Institute of Microelectronics (IME), and its 10 industry partners.

EVG clears key barriers to 3DIC/TSV HVM with fusion wafer bonding solution

06/30/2014  EV Group today unveiled the GEMINI FB XT—its next-generation fusion wafer bonding platform, which combines several performance breakthroughs to move the semiconductor industry closer to the goal of high-volume manufacturing (HVM) of 3D-ICs with through-silicon vias (TSVs).

ConFab panelists discuss optimizing R&D in the changing semi landscape

06/24/2014  Overheard @The ConFab: “I feel the best I’ve felt about semi since 2009.” –Mike Noonen, Silicon Catalyst

SPTS and CEA-Leti/Nanoelec collaborate on 3D-TSV

06/24/2014  SPTS Technologies, a manufacturer of etch, deposition and thermal processing equipment for the semiconductor industry, today announced that it has signed an agreement with CEA-Leti in Grenoble, France, to develop 3D-TSV technologies.

Micron collaborates with Intel on on-package memory solution, leveraging 3D memory technology

06/23/2014  Micron Technology, Inc., a provider of advanced semiconductor solutions, today announced an ongoing collaboration with Intel to deliver an on-package memory solution for Intel's next-generation Xeon Phi processor, codenamed Knights Landing.

GS Nanotech pioneers 3D packaging technology in Russia

06/19/2014  GS Nanotech, microelectronics products development and manufacture center, plans to launch mass assembly of 3D stacked TSV (through-silicon via) microcircuits in next few years.

IEEE Packaging Awards handed out at 2014 ECTC

06/05/2014  The 2014 Electronic Component Technology Conference (ECTC) took place last week in Orlando Florida.

Applied Materials enables cost-effective vertical integration of 3D chips

05/28/2014  Applied Materials, Inc. today introduced the Endura Ventura PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips.

Ziptronix and EV Group demonstrate submicron accuracies for wafer-to-wafer hybrid bonding

05/27/2014  ­ Ziptronix Inc. and EV Group today announced they have successfully achieved submicron post-bond alignment accuracy on customer-provided 300mm DRAM wafers.

SPTS Technologies announces the Omega Rapier XE System for 300mm wafer silicon etch processing

05/22/2014  SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets, today announced the launch of its Rapier XE system for 300mm wafer silicon etching.

Slideshow: What to look for at IITC 2014

05/20/2014  The 17th annual IITC will be held May 21 – 23, 2014 in conjunction with the 31st AMC at the Doubletree Hotel in San Jose, California.

New materials and processes for advanced interconnects

05/16/2014  Although on-chip interconnects have not been scaling at the same speed as other parts of the chip, new capabilities enabled by graphene and CNTs, among other materials, could soon change that.

SRC and UC Berkeley pursue more cost-effective approach to 3D chip integration

05/07/2014  University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

Ziptronix licenses ZiBond to IO Semiconductor for RF applications

04/30/2014  Ziptronix Inc., a provider of patented, low-temperature direct bonding technology for 3D integration, today announced a limited exclusive patent licensing agreement with IO Semiconductor (IOsemi) for application of its ZiBond technology for use in RF front-end devices for consumer mobile products.

STS Semiconductor and Invensas to partner on high volume bond via array mobile solutions

04/22/2014  Tessera Technologies, Inc. announced today that Invensas Corporation and South Korea-based STS Semiconductor & Telecommunications, a semiconductor assembly and test solution provider, have entered into an agreement to validate high volume manufacturing capability for Invensas' Bond Via Array (BVATM) technology for next generation smartphone and tablet customers.

In the permanent bonding market, EV Group is leading, Applied Materials and Tokyo Electron are merging

04/18/2014  Permanent bonding technology is a key process for a wide range of applications in the semiconductor industry such as MEMS, advanced packaging, LED devices, and SOI substrate applications.




FINANCIALS



TECHNOLOGY PAPERS



Parylene 101: Learn about the best protection for MEMS

This paper explains the basic history, processes, and applications of the ultimate conformal coating, parylene. Parylene has historically been used to protect printed circuit boards, LEDS, and medical devices from rugged environments and the human body, but now the pin-hole free coating is being used increasingly by the leaders in the MEMS market. With no known chemical that can harm the film, it is a perfect application for fuel tanks, water meters, or any product that must function in a hazardous environment. May 22, 2014
Sponsored by Diamond-MT

Conformal Coatings for Reliable Electronic Assemblies

Modern electronics have become part of our daily lives and the sophisticated electronic circuitry at the heart of these devices and systems must be reliable. Conformal coatings act as a barrier between the electronics and the environment, protecting the areas they cover while strengthening delicate components and traces. Find out more about how conformal coatings enhance the reliability and longevity of electronic printed circuit boards.April 24, 2014
Sponsored by Master Bond, Inc.,

The Next Step in Diagnosis Resolution Improvement

Learn more about RCD as the next step in diagnosis solution enhancement. Where layout-aware diagnosis points to a segment, earn more about RCD as the next step in diagnosis solution enhancement. Where layout-aware diagnosis points to a segment, RCD can isolate a particular root cause in that segment. RCD, a statistical enhancement technology in Tessent Diagnosis and YieldInsight products, is the next step in diagnosis resolution enhancement. It works by analyzing multiple layout diagnosis reports together to identify the underlying defect distribution that is more likely to explain this set of diagnosis results. RCD does not require any additional data beyond what is required for layout-aware diagnosis. This means that RCD fits well into existing diagnosis flows. April 24, 2014
Sponsored by Mentor Graphics

More Technology Papers

WEBCASTS



Metrology

August 2014 (date and time TBD)

Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions.

Sponsored By:
Advanced Packaging

Sept. 2014 (Date and time TBD)

Back-end packaging is increasingly important to semiconductor device form factor, thermal and power performance, and costs. Compounded by the demand for lead-free processing and the soaring cost of gold, the industry is developing new approaches to packaging, including redistribution layers (RDL), through silicon vias (TSV), copper pillars, wafer-level packaging (WLP) and copper wire bonding. Experts will discuss these and other approaches in this webcast.

Sponsored By:

Interconnects

Oct. 2014 (Date and time TBD)

This webcast will examine the state-of-the-art in conductors and dielectrics, -- including contacts and Metal1 through global level -- pre-metal dielectrics, associated planarization, necessary etch, strip and cleans, embedded passives, global and intermediate TSVs for 3D, as well as reliability, system, and performance issues.

Sponsored By:

More Webcasts

VIDEOS



EVENTS



SEMICON Taiwan 2014
Taiwan
http://www.semicontaiwan.org/en/
September 03, 2014 - September 05, 2014
Vietnam Semiconductor Strategy Summit
Ho Chi Minh City, Vietnam
http://www.semi.org/en/node/46001
September 16, 2014 - September 17, 2014
APC (Advanced Process Control) Conference XXVI 2014
Ann Arbor, Michigan
http://www.apcconference.com/
September 29, 2014 - October 01, 2014