3D Integration

3D INTEGRATION ARTICLES



Applied Materials introduces high-performance ALD technology for the 3D era

07/13/2015  Applied Materials, Inc. today unveiled the Applied Olympia ALD system, featuring a unique, modular architecture that delivers high-performance ALD technology to manufacturers of leading-edge 3D memory and logic chips.

Substrate innovation for extending Moore and more than Moore

07/10/2015  Engineered SOI substrates are now a mainstream option for the semiconductor industry.

IRT Nanoelec partners achieve 3D chip-stacking technology & 3D network-on-chip framework

07/09/2015  IRT Nanoelec, an R&D consortium focused on Information and Communication Technologies (ICT) using micro- and nanoelectronics, and its partners CEA-Leti, STMicroelectronics and Mentor Graphics have realized an innovative 3D chip called “3DNoC” to demonstrate the use of 3D stacking technology in scalable, complex digital systems-on-chip (SoCs).

EMC2015 - New Devices, Old Tricks

06/30/2015  The 57th annual Electronic Materials Conference, held June 24-26 in Columbus, Ohio, showcased research and development (R&D) of new device structures, as well as new insights into the process-structure-properties relationships of electronic devices now running in high-volume manufacturing (HVM) lines globally.

What chipmakers will need to address growing complexity, cost of IC design and yield ramps

06/29/2015  As these early days of the Internet of Things show the network’s promise and reveal technological challenges that could threaten its ability to meet user expectations in the years ahead, technology providers will be charged with supplying the solutions that will meet those challenges.

Solid State Watch: June 19-25, 2015

06/26/2015  IHS says Moore’s Law led to trillions added in global economy; Cadence and Applied Materials collaborate on CMP process optimization; Power transistors seen stabilizing and setting record sales in 2015; Nanowires could be the LEDs of the future

Breaking Down Power Management Verification

06/22/2015  During system-level verification, it is imperative to verify that the software power control applications properly initialize power states and power domains.

3DIC Technology Drivers and Roadmaps

06/22/2015  Circuit performance and silicon area improvements seen in new die stacks.

Leti workshop covers major trends in FD-SOI technologies

06/16/2015  CEA-Leti will host a workshop on major trends in Fully Depleted Silicon-on-Insulator process and design technologies in connection with the 17th annual LetiDays Grenoble, June 24-25.

SK Hynix ramps production of high bandwidth memory

06/16/2015  SK Hynix Inc. announced today that it is shipping mass production volumes of 1st generation High Bandwidth Memory (HBM1) based on SK hynix’s advanced 20nm-class DRAM process technology.

More change for the chip industry

06/11/2015  As if scaling to 7nm geometries and going vertical with FinFETs, TSVs and other emerging technologies wasn’t challenge enough, the emerging market for connected smart devices will bring more changes to the semiconductor sector. And then there’s 3D printing looming in the wings.

ASCENT project offers unparalleled access to European nanoelectronics infrastructure

06/11/2015  Europe’s leading nanoelectronics institutes, Tyndall National Institute in Ireland, CEA-Leti in France and imec in Belgium, have entered a €4.7 million collaborative open-access project called ASCENT (Access to European Nanoelectronics Network).

ISSI agrees to merger terms with Cypress Semiconductor

06/10/2015  Integrated Silicon Solution, Inc. today announced that it has finalized a definitive agreement to be acquired by Cypress Semiconductor Corporation for $20.25 per share in cash.

Move over, 16nm – here comes 10nm chips

06/08/2015  Taiwan Semiconductor Manufacturing wants you to know that they’re ready, willing, and able to help you design chips with 10-nanometer features.

Leti launches new Silicon Impulse FD-SOI Development Program

06/08/2015  CEA-Leti announced today during the Design Automation Conference that seven partners have joined its new FD-SOI IC development program, Silicon Impulse.

Tackling Parameter Extraction for 16nm and Below

06/08/2015  There are four reasons why parasitic parameter extraction is getting a lot harder for 16nm and below technology nodes: 1) 3D device geometries, such as the finFET, which result in more complex electrical fields around the device 2) multi-patterning, which causes increased variability; 3) a demand for 10X tighter levels of accuracy, and 4) increased levels of secrecy from foundries and designers.

A novel characterization technique unveils the 3D structure of conductive filaments in resistive switching memories

06/05/2015  Imec researchers have developed a novel technique – termed conductive atomic force microscopy tomography (or scalpel C-AFM) – that enables a three-dimensional characterization of emerging logic and memory devices.

GLOBALFOUNDRIES solidifies 14nm finFET design infrastructure for next-generation chip design

06/02/2015  GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, today announced it has reached a critical milestone in providing a design infrastructure for its 14-nanometer (nm) FinFET process technology.

Intel CEO looks to 3D tech at display conference

06/02/2015  Intel CEO Brian Krzanich touted the capabilities of his company’s RealSense technology in a keynote address at the Society for Information Display conference in San Jose, California.

Silicon Technology Extensions shown at MRS Spring 2015

06/01/2015  New ultra-fast crystallization using lasers or plasma-jets.




TWITTER


FINANCIALS



TECHNOLOGY PAPERS



How Software Can Impact Your Processes and Maximize Profit

View this paper to learn how Epicor ERP specifically aligns to the business needs of the electronics and high-tech industry, and hear how one electronics organization achieved improved operational controls, better inventory accuracy, and world class tools to meet supply chain requirements with Epicor ERP.July 01, 2015
Sponsored by Epicor

Three Key Factors to Create Leak-Free Fitting Assemblies for Fluid Processing Applications

Operational efficiency is a critical factor in the fluid processing industry. The synergy of fitting components and assembly technology to achieve this objective is the focus of Fit-LINE, Inc. Applying extensive polymer technology and injection molding expertise, the company has analyzed the design, tooling and manufacturing processes required to create high-performance solutions for demanding high-purity fluid processing applications. Through extensive R&D, testing and evaluation, Fit-LINE has isolated three variables that need to be addressed to ensure leak-free fitting assemblies.June 01, 2015
Sponsored by Fit-LINE, Inc.

Silicones Meet the Needs of the Electronics Industry

Remarkable silicones. The combination of their unique ability to maintain physical properties across a wide range of temperature, humidity, and frequency--combined with their flexibility--set them apart. Silicone based adhesives, sealants, potting and encapsulation compounds are used in hundreds of consumer, business, medical, and military electronic systems. In this white paper, learn what makes silicones different from other organic polymers, why their properties remain stable across different temperatures, and how they have played a major role in the rapid innovation of the electronics industry.May 12, 2015
Sponsored by Master Bond, Inc.,

More Technology Papers

WEBCASTS



System Scaling and Integration Platforms for Mobile Devices and IoT

September 9, 2015 at 8:00 p.m. ET

In this presentation, recent developments in interconnects and packaging technologies that will enable mobile devices, and IoT will be discussed. Some of these packaging technologies include high density fan-out wafer level packaging, passive and active interposers, high throughput chip-on-wafer bonding, as well as wafer level chip scale packaging for MEMS and sensors.

Sponsored By:
Metrology

September 2015 (Date and time TBD)

Continued scaling and more complex device structures, including FinFETs and 3D stacking, are creating new challenges in metrology and inspection. Smaller defects must be detected and analyzed on an increasingly diverse set of materials. Chip makers are looking for better wafer edge inspection techniques, higher resolution metrology tools, 450mm-capability and new compositional analysis solutions. Experts will describe new approaches for next generation metrology and inspection, including measurements of CDs, stress, film thickness and non-visual defects.

Sponsored By:

Lithography

September 2015 (Date and time TBD)

EUV lithography has been under intense development for years and appears to be close to production. Yet its delay has the industry searching for alternatives, including double, triple and even quadruple patterning, directed self-assembly, multi-e-beam and nanoimprint. In this webcast, experts will detail various options, future scenarios and challenges that must still be overcome.

Sponsored By:

More Webcasts

VIDEOS



EVENTS



European MEMS Summit
Milan, Italy
http://www.semi.org/eu/node/8871
September 17, 2015 - September 18, 2015
SPIE Photomask Technology 2015
Monterey, CA
http://spie.org/x6323.xml
September 29, 2015 - October 01, 2015
SEMICON Europa 2015
Dresden, Germany
http://www.semiconeuropa.org
October 06, 2015 - October 08, 2015
International Electron Device Meeting 2015
Washington D.C. United States
http://www.his.com/~iedm/
December 07, 2015 - December 09, 2015
2015 IEEE World Forum on Internet of Things
Milan, Italy
http://sites.ieee.org/wf-iot/
December 14, 2015 - December 16, 2015