A Dirty Job: The Challenge of CMP
Chemical Mechanical Polishing (CMP) is fast becoming the established technology for planarizing metal and interlayer dielectrics of multilevel sub-0.5 ?m devices, with projections of six layers of metal by the year 2000. An inherently OdirtyO process, wafer fabs are racing to contain it, automate it, and integrate it into Class 1 cleanrooms.
By Susan English
Evolution of devices and market demand are bringing CMP “out of the basement” and into the cleanroom. Driven by the needs of the semiconductor industry for planar wafers across the die and across the wafer, CMP–Chemical Mechanical Polishing, or Planarization, as the terms are used interchangeably these days–has emerged as the technology of choice among semiconductor manufacturers, offering exemplary capabilities below 0.35 µm. No longer restricted to microprocessors and other logic devices, it is being applied to the production of DRAMs and even ASICs, and is outpacing both the semiconductor and the wafer fab equipment markets, according to figures from DataQuest (Santa Clara, CA). Total tool integration, robotics, environmental enclosures, and even SMIF capabilities–evolutionary steps common to other IC fabrication processes–are expected to reverse the trend to wall-off CMP from other areas of the fab and bring it into the “front end” of the process and inside a Class 1 cleanroom, say the experts.
The race toward total tool integration and the ultimate integrated tool– “dry wafer-in/dry wafer-out”– is pushing suppliers of polishers, cleaners and other CMP components to form working partnerships to produce integrated solutions. Slurry companies are partnering with polisher manufacturers; companies like San Jose-based OnTrak Systems, Inc., are proclaiming “open architecture” strategies, and manufacturers of wafer cleaners are seeking out polisher-makers. Many suppliers will be displaying the outcomes of such joint efforts this month at Semicon West (July 16-18, San Francisco, CA). Among them is IPEC Planar (formerly Westech Systems) in Phoenix, AZ, which is introducing a fully integrated CMP planarizing/cleaning system, the Avanti 672. According to IPEC, the 672 is the first to offer 300-mm wafer capability in Dry Wafer Out (DWO) system configuration with a Class 1 wafer trail, incorporating full robotics with SMIF compatibility.
In a semiconductor market shooting towards $300 billion by the year 2,000, CMP equipment sales of over $200 million are projected by 1997, according to statistics compiled by the CMP Users Group at VLSI Technology, Inc. (San Jose, CA). The Information Network, a Williamsburg, VA-based market research company, predicts a total worldwide market of $1.48 billion for CMP modules by 1999. While the CMP equipment market has been largely confined to the U.S., with most CMP equipment sales in Europe going to U.S.-owned fabs, Europe and the Far East are rapidly turning to the advantages of CMP for use in logic manufacturing. In Europe, JESSI has inaugurated a program with several European equipment vendors to develop a clustered CMP tool. The only technique currently available for global planarization below 0.35 µm, CMP is also expected to experience strong market growth in Japan and Asia-Pacific, where submicron developments are proceeding apace.
The sub-half micron geometries of today`s integrated circuits have created an entirely new set of challenges in the patterning, deposition and etching of thin films. Increased packing densities, higher aspect ratios and multi-level metal structures have resulted in greater surface topography variations, as well as different contact/via step heights–making it more difficult to achieve optimum photolithographic resolution, narrow gap fill and contact/via resistance. To overcome these difficulties, global planarization–leveling the entire surface of the die or wafer rather than just specific portions–has become a critical process step not only to meet the depth-of-focus requirements for deep submicron lithography, but also to improve step height coverage, metal reliability, speed and yield. First developed at IBM, CMP was an in-house technology for many years, the disadvantages are the inherently “dirty” nature of the process, particularly the polishing pads and slurries. The major areas of concern for contamination control specialists are the CMP process itself, including post-CMP cleaning, the consumables–pads and slurries–cleaning and polishing equipment and the environment. Polishing consumables come in direct contact with the wafer surface and make up the bulk of the contaminants that impact overall wafer cleanliness following post-CMP clean.
The CMP process
The CMP module can be divided into four essential parts:
1. The polishing machine, which includes the platen, vacuum system, wafer carrier, rotor motor and alignment system;
2. The consumable materials–carrier plastic film, the chemical slurry, and the polishing surface or pad;
3. The post-CMP cleaning system, which is used to scrub away traces of chemicals and surface contamination;
4. Process diagnostics.
During CMP, the back side of the wafer is attached to a plastic film held inside a rotating carrier. The front side of the wafer is then pressed against a textured pad soaked with an abrasive slurry–a very fine powder in liquid suspension. Simultaneous chemical and mechanical actions are applied to the surface of the wafer, removing 0.2 µm to 2 µm of material. To remove metal from the wafer, metal slurries use an oxidizing agent. For oxide polishing, a stress corrosion mechanism utilizing chemistry and pH–stress-drive dissolution of the oxide–helps planarize it. After planarization, the wafer is taken to a cleaning system for the post-CMP clean, where residual slurry and other CMP by-products are removed. If not removed, residual slurry will introduce particles, metal contaminants and chemicals into the remaining stages of chip fabrication. It has been said that the CMP process involves a trade-off between polishing goals (uniformity, planarity, throughput) and cleaning goals (reduced defects and surface damage).
CMP slurries can vary significantly from fab to fab because of proprietary mixes and additives. Cross-contamination and dried slurry lead to wafer defects and low production yield, therefore, a great deal of contamination control effort is expended on “slurry control.” Dried slurry clogs tools and chemical distribution systems. Cross-contamination of other areas of the fab is a real hazard, too, since particles can be carried out on wafers, carriers, boxes or personnel leaving the CMP production area. Slurry must be kept suspended in aqueous solution, continuously recirculated or agitated by diaphragm pumps through a loop to keep solids from precipitating out. If allowed to harden, it must be scrubbed off using a polisher or brush. Although CMP slurries are composed of very fine particles of up to 300 nm (0.3 µm), large particles of 5 µm and greater are often present at the point of distribution and dispensing lines to the polishing tools and must therefore be filtered out. These can occur as a result of agglomeration–the presence of foreign material or precipitation.
Slurry particles can scratch and gouge wafer surfaces during polishing, causing metal shorts. Filters at slurry distribution and dispense points should be made of continuous, bonded fibers that do not release particulate or fibrous material of their own or unload captured contaminants.
Tool clustering/integration and containment
During grinding and polishing–the messiest operations–contamination control efforts center on keeping particles confined within the tool itself so as not to contaminate the rest of the cleanroom environment. Wafer polishing is sometimes performed in “polish farms” with separate air systems. Polish areas may also be located in a basement, a separate building, in adjacent old fabs or even attached as separate areas isolated by a wall or curtain. Foot traffic to and from these areas to the main fab area is usually limited or excluded, and garments must be changed before leaving one area for another. Other fabs utilize controlled chase areas, or “gray” zones, where wafers can be kept away from particle generators like the polishers/scrubber modules.
While both tool clustering–grouping a cleaning station with polishing tools or other CMP process equipment–and tool integration is evolving amongst much debate, all involved agree that process environments should be properly managed to control cross-contamination and environmental conditions that affect the process. In an article entitled “Managing CMP Contamination with Environmentally Enhanced Enclosures,” Chris Young, principal research scientist at Intelligent Enclosures Corp. (Norcross, GA), talks about the hazards of slurry and other chemicals in the CMP process environment. He proposes an enclosure system to properly manage and control cross-contamination, provide protection of personnel against noxious chemicals and vapors, and environmental conditions.
Young says that “many or most” CMP tool suppliers incorporate some type of enclosure or hood system to contain slurry and chemical vapors. He cites laminar-filtered airflow, dynamic chemical exhaust, high relative humidity control and engineered airflow design as requisite for proper control of cross-contamination. A standard polisher tool configuration incorporates filtered air supply only to the I/O area to protect staged wafers with positive air pressure. The polishing process area may be kept at a negative pressure using facility exhaust to remove any chemical vapor contamination. But operating a CMP tool enclosure with negative pressure allows infiltration of fab-generated contamination into the process area and sends excessive and unnecessary volumes of air to the fab scrubber.
A polisher located in a gray area has an increased chance for contamination from the degraded environment, and macroscopic wafer defects are typically caused by large particles entering the polishing chamber. Lack of airflow management can also result in adverse air flow conditions over the polishing pads. Excessive air turbulence can lead to slurry contamination problems. Young says that laminar flow air should be supplied to the CMP tool process area at very low velocity to provide a flow path for any airborne contamination to exit the process area and be captured in the enclosure filters. Low air velocity also minimizes turbulence and drying of the slurry. The I/O area of the tool can then be supplied with filtered air at a higher velocity and pressure.
Relative humidity has been found to have the greatest effect on the slurry-drying rate, with 70 to 90 percent relative humidity being optimum. In an operational fab, where slurry delivery lines frequently become clogged, a high humidification controlled enclosure system is usually installed. Air temperature must also be controlled to avoid reaching dew point conditions within the enclosure system.
CMP cleanliness standards
Although a lot of people are spending time characterizing the CMP process empirically, “there`s not much understood about the science aspects of it,” according to Dale Hetherington of Sandia National Laboratories (Albuquerque, NM), who says that the central research hub for CMP continues to be Sematech. Last July, a two-day symposium–the second Semiconductor Research Corp. Topical Research Conference on CMP–was held at Rensselaer Polytechnic Institute (RPI) in Troy, NY, the site of the New York Sematech Center of Excellence for multilevel metallization. A special breakout session on CMP standards included the subject of cleanroom facilities specifications “to delineate contamination control issues within the CMP area and cross-contamination with other areas in the fab.” Although the topic was canceled due to time constraints, Dr. Michael Fury, a key participant, recommended that participants review existing SEMI standards on a variety of related topics for elements relevant to the CMP operation and interaction with adjacent areas in the fab.
With almost a complete absence of standards or clean protocol, fab companies have been improvising the process, by and large adapting it to existing conditions in their fabs. According to RPI`s Ron Gutmann, “the policy is `keep the wafer wet until it`s clean,`” following process immediately with different types of brush cleaning and liquid cleaning and then dry.” Sharon Laskanic, a National Semiconductor (Santa Clara, CA) assignee at Sematech, recently completed work on a pilot CMP line for National Semiconductor`s 200-mm fab, now under construction in South Portland, Maine. Says Laskanic, “Class 100 or 10 is sufficient, because the key thing is that once you polish, you want to clean; and once wafers are cleaned, that`s when it`s important to keep them in the cleanroom environment. In this way, you eliminate a lot of the costs of putting the CMP operation in a Class 1 area.”
Although considered an inherently “dirty” process, CMP is more and more being contained and approached as just another fab process, says Angelo Rapa, director of contamination control technology at Jacobs Engineering (Portland, OR) formerly of IBM: “The initial view of chem-mech polish is that since it`s a dirty operation, you put it in a dirty area. In reality, it`s a contamination-sensitive operation like any other. Slurry is a very controlled chemical, and like any other semiconductor process, chemical and like any other semiconductor process it needs to be performed in a controlled environment. It has some special concerns, but it also needs to be looked at for contaminants,” he says.
Process contamination control
Motorola APRD`s (Austin, TX) CMP manager, Kathleen Perry, says some people believe it`s acceptable to put the CMP tools and bays in the same cleanroom environment. “Then there`s another view that says, `Do you really need the same class of cleanroom for your CMP, or can you make it a separate less rigorous section with different air ventilation and simply have the wafers, when they come out of the cleaners, go to the clean environment.` A third approach is enclosing your CMP tool. You can put it in any kind of dirty area, but put a minienvironment around it.”
Peter Burke at AMD`s Fab 25 in Austin describes four basic approaches (see figures A-D, page 18). One is to install the polisher in the Class 1 clean area–an expensive option that would require constant monitoring, “which people probably wouldn`t do,” he says. A second approach is to install the polisher in a Class 10 or Class 1,000 area. “Then in front of the polisher, where all the clean tools are, is your Class 1, and you just deal with dripping water on the floor as best you can.” A third approach would be to have the whole polish area and all the film thickness material in Class 1,000. A fourth option is to consider the whole area “dirty” and clean or scrub particles off wafers when they are sent back to the fab. “When people expand or upgrade a fab, and they add polish at the same time, for instance, they`ll keep the polisher under the old air-handling systems and then just add on the clean part. And the rest of the fab is all upgraded for cleaning,” he says.
Burke describes Option 4 as the trickiest due to the lack of good information flow. “You have to take individual wafers out, which is always going to create scratches and defects that inhibit the metrology,” he points out. “And the feedback on how clean your wafers are coming out rarely gets back to the polish area in a timely fashion. So if you`ve got a polisher that`s got gross bacteria in it, you don`t know until much later.” Contamination of wafer cassettes is also an issue, says Burke.
Mark Aubuchont worked with Digital Semiconductor (Hudson, MA) as principal equipment engineer, designing and laying out the CMP area for Fab 6 in Hudson, MA in 1993. Currently, he is East Coast regional sales manager with SpeedFam Corp., based in Chandler, AZ, which produces the CMP-V planarization system. Digital`s ballroom cleanroom has divider walls separating its CMP-V`s from the Class 1 area containing the cleaner and metrology equipment. The Class 10 service corridor or gray area has full 100 percent ULPA coverage, although Aubuchont says, they don`t try to maintain it at that level in the chem/polish area, which is segregated from the rest of the fab. “The normal process, when you come out of the polisher–if you don`t have an integrated cleaner–is that you more or less have to carry around a wet dripping cassette–some people use a bucket, others, a little cart that you roll over to it–that is wet and keeps the wafers wet. Some people just walk it from the polisher, turn and set it on the cleaner, which means that you`re dripping slurry water on the floor and everything else. It`s really important that the wafer cassettes stay within the CMP area and don`t get out into the fab area. It`s also important that the output cassettes stay either with the input of the cleaners or the output of the polishers, and the same is true on the other end, where the cassettes that are used for the wafers in the input of the polisher and the output of the cleaners are segregated from what has been wet, because it will have the slurry particles on it.”
Rodel, Inc. (Newark, DE) marketing expert Dr. Michael Oliver, recommends that new users “start from scratch” by keeping separate cleanroom garments, separate wafer boats, separate personnel entry for the CMP area, just as for other process areas. “The fact that tool manufacturers are starting to integrate the first pass clean right in the tool contributes to dispelling the myth that you need to have it totally segregated.” He says, “I think that most people`s initial concerns have died away, because in reality–especially for metal CMP–the actual implementation of it improves yields rather than harms yields. Whatever the risk of particles is overshadowed by the inherent gain the process brings to the overall semiconductor fabrication process.” n
Editor`s Note: This year, the first meeting of the new CMP task force will be held this month during Semicon/West `96. Industry professionals will be invited to voice concerns on what aspects of CMP should be standardized, what the scope of the group should be, and what standards should be developed for the CMP industry.
SpeedFam`s CMPV polishing tool with heads retracted and polish table in the foreground.
Polishing pads and slurry manufactured by Rodel, Inc. for polishing silicon wafers during chemical mechanical polishing (CMP).
SpeedFam`s CMP-V Planarization System includes five independently controlled polishing heads, on-board double-side wafer scrubber, optional second polish table, cascading DI index table, wet output elevators with DI overflow, automatic liner rinse, and slurry containment system for post-polish wafer output. Cassette-to-cassette automation eliminates operator handling and minimizes process dead time between polish cycles.
The accompanying figure shows four possible cleanroom layouts for polishing areas.
In Figure A, the entire CMP operation is located in a Class 1 cleanroom. The advantages are that no second clean in the fab is necessary, and there is flexibility to rearrange polishers. Disadvantages to this layout are that Class 1-or-better polishers are “overkill”–too expensive–constant monitoring is necessary. Several potential cross-contamination issues exist, as well as the need for a tight polish area protocol. A few options are to have the CMP operation remote from the main fab or else attached directly; to use a separate wall or unsegregated cassette handling, or to maintain a Class 1 gray area separate from the clean area.
In Figure B, the polishers are bulkhead-mounted in the “gray area,” (Class 100 to Class 1,000). Cleanroom space is less expensive than in Figure A, and no second clean is needed in the main fab. Disadvantages are a lack of flexibility in layout, tight polish area protocol and many cross-contamination issues.
In Figure C, the entire CMP operation is in a Class 100-1,000 cleanroom. A second clean is performed in the main fab. The advantages here are cheaper cleanroom space, looser polish area protocol, and less risk of subsequent main fab tool contamination. The disadvantages are capital expenditures for the second CMP clean in the main fab and the inherent risks associated with shipping dirty wafers to the main fab.
In Figure D, the entire CMP operation is in a Class 100-1,000 cleanroom, with the CMP operation adjacent to the fab. All cleans are performed in the main fab. As in Figure C, the big advantage is low-cost cleanroom (polish) space. Because only one clean is performed, there is also low risk of subsequent main fab tool contamination, and protocol in the polish area can be loose. Disadvantages are capital expenditures for sample wafer cleaning and redundant metrology, the control difficulties of maintaining two separate areas for determining CMP cleanliness and product defect feedback, as metrology becomes problematic.
Figure and caption written by Peter Burke, a senior MTS at Advanced Micro Devices, Fab 25 (Austin, TX).
Minienvironments by Intelligent Enclosures integrate an automated exhaust system around the polishing tool, and are designed to manage and control slurry, cleaning solutions, chemical vapors, equipment-related contamination and fab-generated contamination.
CMP is used for global oxide planarization to eliminate the additive effect of topography variations as layers are stacked. The most common CMP applications are polishing the oxide layers above and below the first metal layer.
Credit: Tencor Instruments (Mountain View, CA)
CMP is also emerging as a solution for planarization of tungsten layers– a useful alternative for devices with random patterns that leave difficult-to-fill via holes.
Credit: Tencor Instruments (Mountain View, CA)