Implications of damascene topography for electroplated copper interconnects

As-electroplated copper undergoes a gradual recrystallization at room temperature related to the plating chemistry. The influence of damascene topography on the recrystallization as well as on the texture of Cu must be understood to optimize properties for superior interconnect performance. A low-temperature anneal before CMP stabilizes the Cu microstructure and eliminates the (111) sidewall growth component that is observed if the overlying Cu is removed before recrystallization.

The introduction of Cu metallization in advanced 0.18µm-generation integrated circuits (ICs) involves a revolutionary change in process architecture for multilevel interconnects. In contrast to conventional Al interconnects that are defined by a subtractive metal etch of a planar Al film, the geometries of Cu interconnects are defined by trenches and vias etched in the dielectric that are subsequently filled with metal (Fig. 1). Damascene processing avoids the problems associated with etching Cu, but a challenge of a different sort arises from the need to fill these high aspect ratio dual damascene structures without voids in the metal.

Figure 1. Schematic of subtractive-Al vs, damascene-Cu fabrication processes. Arrows indicate direction of film growth and possible orientation of texture in the interconnect metallization.
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Line-of-sight physical vapor deposition (PVD) techniques are inadequate for filling such features. Accumulation of deposits at the upper corners of trenches leads to pinch off and void formation. Chemical vapor deposition (CVD) has the potential for conformal coverage, but numerous chemical and hardware issues have hampered development of a manufacturable fill process. Thus, to the surprise of many in both the semiconductor and plating industries, electroplating has emerged as the deposition method of choice for damascene Cu interconnects [1]. Advanced sputtering techniques are still needed, however, to deposit a thin barrier film (Ta, TaN) and a conduction layer of Cu before plating.

In this paper, we review recent investigations aimed at understanding how damascene topography influences Cu metallization with respect to the electroplating process, the room temperature recrystallization of the resulting film, and the crystallographic texture of the Cu interconnects formed in trenches.

Topography and electroplating

The ability to achieve superior void-free filling of damascene structures for sub-0.18µm technology by electroplating is largely due to the influence of additives in the plating bath. Additives for acid Cu plating were originally developed to enhance the brightness and hardness of deposits; both of these attributes can be related to decreasing the grain size of the deposits and reducing (or leveling) the topography over rough surfaces.

Manipulation of the Cu sulfate/sulfuric acid electroplating process through additives is highly advantageous for submicron interconnect applications. In the absence of additives, the grain size of the Cu is roughly 1µm and the film surface is rough. Additives lead to a much finer (<1000Å) grain size and a smooth, highly reflective surface that has significantly less topography than the underlying substrate.

The leveling effect of the additives provides one of the major advantages of electroplating for interconnect applications [2, 3]. Cross-section micrographs of trenches at intermediate stages of fill during plating are shown in Fig. 2. The deposition profiles show a super-conformal (or “bottom-up”) fill with little build up at the upper corners that would lead to pinch off and void formation. As the trenches are filled, the surface topography is leveled to provide a more uniform field for subsequent chemical mechanical polishing (CMP).

Figure 2. FIB cross-section images (at a 45° sample tilt) of electroplated Cu showing progression of fill profile and topography during plating in 0.9µm deep trenches. 500TaN and 1000Å Cu (as measured on field) were sputtered on before plating. Trench widths are 0.17µm (a-d) and 0.30µm (e-h).
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The plating baths for interconnect applications currently include a combination of proprietary additives that are generally categorized by function as levelers, brighteners, and carriers. The levelers and brighteners consist of sulfur and nitrogen-functionalized small organic molecules and salts that interact with the cathode (wafer) surface and are highly effective at low concentrations in solution. Carriers are typically polymers such as polyethylene glycol that influence the transport properties in the boundary layer. Cl- is added to the bath in higher concentrations and influences the plating by complexing cuprous and cupric ions. The mechanisms by which the multiple additives interact and influence plating at the wafer surface are not well understood. Additional interactions of additives at the consumable Cu anode are also not well understood. Nevertheless, it is clear that the additives affect both the nucleation density and the growth of grains.

Further complicating the situation is the depletion of additives that occurs during plating – by incorporation into the film or by electrolytic decomposition – which produces additional species in solution. But this depletion is important for bottom-up fill. The suppression of plating at the upper corners of the trenches and in the regions between trenches is maintained by constant replenishment of the additives that block surface sites. The fluid dynamics in the submicron-scale trenches, combined with the low additive concentrations, produce a net depletion of plating suppressors inside the trenches, resulting in reduced suppression of plating and faster deposition rates from the bottom corners up [3, 4]. Localized depletion of Cu ions inside the trenches is not a problem because of the much higher overall Cu concentration in solution. Thus, there will be a minimum in suppression of the plating rate within the trenches, and a maximum at the upper corners of the trenches where the flux of additives is highest. While the additives play a central role in achieving superior fill profiles, they also influence the materials properties of the plated Cu.

Topography and recrystallization

An unexpected aspect of the electroplated Cu process is the change in film structure and properties after plating. Over a period of hours to days, a remarkable recrystallization occurs at room temperature during which the as-plated ~1000Å grain size increases to several microns [5-10].

This phenomenon had been previously reported for blanket films and associated with defects, dislocations, and/or strain in the small-grained films caused by additives in the plating baths [6]. The strong influence of the additives in suppressing plating at the upper corners of trenches suggests a possible correlation with the recrystallization process [8]. The large-grained deposits from the additive-free bath do not undergo this recrystallization.

Figure 3. FIB plan-view images (left) of 1µm electroplated Cu over 5.0/5.0µm trench/space gratings (0.5µm deep) and corresponding cross-sectional schematics (right), showing the evolution of recrystallization starting at upper corners, proceeding across the trenches, and finally moving between them.
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FIB imaging offers a convenient way of monitoring the changes in the film during grain growth (Fig. 3). Individual grains of different crystallographic orientation can be distinguished as a result of the channeling contrast afforded by the Ga+ beam as it penetrates the sample. In these images, a 1µm Cu film was plated over an array of 5µm trench/space gratings that are 0.5µm deep. The surface is not fully planarized over these wide trenches and the surface topography can be seen as alternating darker (trench) and lighter (field) stripes.

The correspondence between the sites where large grains first appear and the underlying topography revealed in the planview FIB images (Fig. 3) is of interest from a mechanistic perspective. In the initial stages of recrystallization, we see the large grains nucleate in linear arrays aligned with the upper corners of the trenches. Once nucleation has occurred at these upper corners, recrystallization proceeds across the trenches before extending between them. The large size of the recrystallized grains relative to submicron trench widths makes it difficult to see a correspondence of nucleation sites with topography for submicron trenches.

The progression of recrystallization across the trenches and then between the trenches can in part be explained by the difference in Cu thickness in these two regions, with the thicker Cu inside trenches recrystallizing at a faster rate. However, for equal trench/space gratings in which the trenches comprise 50% of the surface in all the samples, we still see a variation in recrystallization times with line width (Fig. 4). Quantitative data for recrystallization times are extracted from analyses of plan-view FIB images as the fraction recrystallized, making the assumption of a linear correlation between the areal images and the three-dimensional volume recrystallization [7].

The data in Figure 4 reveal a minimum in recrystallization time for the intermediate 0.8µm trench width. These data were collected from samples that were kept chilled on dry ice after plating to prevent recrystallization until measurements could be made. Similar trench width dependence has been observed for as-plated samples that were not cycled to low temperature, but the factor of 10 increase in rate for the temperature-cycled samples suggests a stress component in the recrystallization process.

Figure 4.Recrystallized fraction vs. time for different trench width gratings (0.5µm deep) with 1.0µm electroplated Cu that was cooled to -78°C and then allowed to recrystallize at room temperature without CMP. Substrates were patterned PETEOS-SiO2 with 500Å and 1000Å PVD Cu.
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It is clear that the additives in the plating bath are also involved, directly or indirectly, in the recrystallization process. The inclusion of impurities at grain boundaries from the additives or their electrolytic byproducts would be expected to cause pinning that would suppress grain growth. This is borne out in a report comparing the rates of recrystallization of samples from baths with different additive concentrations; slower rates of recrystallization are observed for films deposited from baths with higher additive concentrations [11]. Yet comparing films deposited from plating baths without and with additives, it is only in the latter case that we observe grain growth.

Up to a certain concentration, additives may influence the formation of defects and/or dislocations in the films that drive the room temperature recrystallization. At some point, pinning by higher concentrations of impurities at the grain boundaries may outweigh this effect.

The upper corners of the trenches, where we observe the nucleation of recrystallization, are also the sites where the additives have had a strong influence during plating in suppressing deposition. This would suggest an indirect influence of the additives on recrystallization through formation of more defects, dislocations, and/or stresses at these sites, rather than directly through higher impurity incorporation.

The minimum in the recrystallization rate for intermediate trench widths may then be related to the relative density of high-defect regions. At the smallest trench widths, the overlap between these regions may create a relatively uniform distribution of defects, while at the largest widths the upper corners are sufficiently separated to appear as discrete steps. At the intermediate widths, there may be the highest net variation in defects across the wafer. Additional data on the influence of spacing and depth on recrystallization rates, and changes in the sheet resistance, stress, and hardness that accompany recrystallization have also been reported [7, 10-12].

Another interesting feature of the recrystallization process is the absence of any seams in the trench where the growth fronts from the bottom and sides meet (Fig. 2). There is also no indication of a discrete 1000Å PVD Cu layer (deposited over the Ta barrier before plating), indicating that recrystallization incorporates all of the Cu inside the trenches. An abundance of twin boundaries (parallel, high-contrast regions) visible in the larger grains are indicative of the low stacking fault energy in Cu. They also point to the involvement of twinning as a factor in the grain growth process and evolution of texture [13, 14].

Recrystallization and texture

X-ray diffraction pole figure measurements are important for determining the crystallographic texture of polycrystalline films. By this technique, all grains are analyzed regardless of orientation, whereas the more routinely used q-2q measurements sample only those grains whose crystallographic planes are parallel to the surface. This is of particular importance in analyzing samples with significant topography, as in damascene Cu structures.

Electroplated Cu deposited on an unpatterned wafer with SiO2/PVD Ta barrier/PVD Cu conduction layer stacks exhibits a strong (111) texture as-plated that diminishes significantly after room temperature recrystallization [15, 16].

If Cu grows with equally strong texture on the vertical as well as the horizontal surfaces inside the damascene trenches, – and in a nondirectional deposition process such as plating, this would be expected – we should see a sidewall growth component in the pole figures of the Cu in the trenches. As is evident in the sequence of partial fill FIB cross sections in Fig. 2, Cu plating proceeds from the sidewalls as well as the bottom of the trench.

A sidewall growth component would appear as intensity at ±90° from the central pole in the (111) pole figure, corresponding to the (111) poles perpendicular to the two sidewalls. Note that the orientation of underlying films (i.e., the diffusion barriers) in multilayer polycrystalline stacks may also influence the texture of the overlying films. Differences in the texture and morphology of both the sputtered Ta barrier layer and the sputtered Cu conduction layer between surfaces parallel or perpendicular to the sputtering target might, therefore, influence the texture of the electroplated Cu. To examine the texture of only the Cu in the trenches, overlying Cu was removed by CMP before the pole figure measurements. The order in which the CMP and recrystallization took place, i.e., the presence or absence of the overlying Cu during recrystallization, had a significant influence on the texture of the Cu in the submicron trenches.

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Figure 5. Contour plots of (111) pole figures for 1.0µm electroplated Cu in 0.3µm wide by 0.5µm deep trenches after CMP, and cross-sectional schematics showing the influence of overlying Cu on the recrystallization texture of the Cu in the trenches. a) Large-grained Cu recrystallized at room temperature before CMP follows the overlying texture; b) small-grained as-plated Cu (stored on dry ice until CMP); and c) large grained Cu after annealing the sample in b) in forming gas at 400°C for 30 min showing (111) texture with a sidewall growth component. Substrates were patterned PETEOS-SiO2 with 500Å PVD Ta and 1000Å PVD Cu; contour levels are in logarithmic intervals and the trench direction is from left to right.

Figure 5 shows the complete (111) pole figures for Cu in 0.3µm trench/space gratings that are 0.5µm deep, comparing the cases where the Cu was allowed to recrystallize before or after CMP. For the case where recrystallization was allowed to proceed before the overlying 1µm of Cu was removed by CMP, we see no evidence of a sidewall component (Fig. 5a). If the overlying Cu is removed by CMP while still in the as-plated small-grained state, the resulting pole figure of the small-grained Cu in the trenches reveals a sidewall component (Fig. 5b); this component is still present after the same sample is annealed in a furnace to 400°C for 30 min in forming gas (Fig. 5c). These observations indicate that if Cu is allowed to recrystallize before CMP then the texture of the larger volume of overlying Cu dominates the texture in the trenches.


The time-dependent variations in the electroplated Cu film properties and the influence of damascene topography on recrystallization and texture have been characterized. Conflicting observations on recrystallization rates in the literature highlight the role of additives and the necessity of understanding their mechanisms of interaction [7-11]. The additives that afford good damascene fill and leveling also fortuitously provide us with a low-temperature route to the large grains and reduced grain boundary volume that are desirable for improved electromigration resistance.

In a manufacturing process flow, a low-temperature anneal step will be introduced after plating and before CMP to stabilize the materials properties and maximize throughput. This will also lead to the elimination of the sidewall texture component.


  1. D. Edelstein, et al., IEEE Intl. Electron Devices Meeting Digest, 773, 1997.
  2. P.C. Andricacos, C. Uzoh, J.O. Dukovic, J. Horkans, H. Deligianni, IBM J. Res. Devel., 42, 567, 1998.
  3. M.E. Gross, K. Takahashi, C. Lingk, T. Ritzdorf, K. Gibbons, in Adv. Metalliz. Conf. 1998, ed. G.S. Sandhu, H. Koerner, M. Murakami, Y. Yasuda, N. Kobayashi, Mater. Res. Soc., Pittsburgh, PA, pp. 51-56, 1999.
  4. K.M. Takahashi, M.E. Gross, in Adv. Metalliz. Conf. 1998, ed. G.S. Sandhu, H. Koerner, M. Murakami, Y. Yasuda, N. Kobayashi, Mater. Res. Soc., Pittsburgh, PA, pp. 57-63, 1999.
  5. In the literature, the terms grain growth and recrystallization are often used interchangeably when referring to these phenomena in secondary mode.
  6. I.V. Tomov, D.S. Stoychev, I.B. Vitanova, J. Appl. Electrochem., 15, 887, 1985.
  7. T. Ritzdorf, et al., in Intl. Interconnect Technol. Conf. Abstracts, pp. 166-168, San Francisco, CA, June 1998.
  8. C. Lingk, M.E. Gross, J. Appl. Phys. 84, 5547, 1998.
  9. C. Cabral, Jr., et al., in Adv. Metalliz. Conf. 1998, ed. G.S. Sandhu, et al., Mater. Res. Soc., Pittsburgh, PA, pp. 81-87, 1999.
  10. Q.-T. Jiang, K. Smekalin, in Adv. Metalliz. Conf. 1998, edited by G.S. Sandhu, et al., Mater. Res. Soc., Pittsburgh, PA, pp. 209-215, 1999.
  11. T. Ritzdorf, L. Chen, D. Fulton, C. Dundas, in Intl. Interconnect Technol. Conf. Abstracts, pp. 287-289, San Francisco, CA, June 1999.
  12. M.E. Gross, et al., MRS. Symp. Proc., 564, Advanced Interconnects and Contacts, ed. D. Edelstein, T. Kikkawa, M. Ozturk, K.-N. Tu, E. Weitzman, Mater. Res. Soc., Pittsburgh, PA, in press, 1999.
  13. A. Berger, et al., Prog. Mater. Sci., 32, 1, 1998.
  14. C. Lingk, M.E. Gross, W.L. Brown, unpublished results.
  15. C. Lingk, et al., in Adv. Metalliz. Conf. 1998, ed. G.S. Sandhu, et al., Mater. Res. Soc., Pittsburgh, PA, pp. 73-79, 1999.
  16. C. Lingk, M.E. Gross, W.L. Brown, Appl. Phys. Lett. 74, 682, 1999.


M.E. Gross is a member of the technical staff at Bell Labs, Lucent Technologies, Murray Hill, NJ 07974; ph 908/582-4504, fax 908/582-2300, e-mail

C. Lingk is a PhD student at the University of Munich, doing research in the field of optoelectronics.

W.L. Brown is the head of the thin-film metals and dielectric research department at Bell Labs.

R. Drese is working toward his Diplom degree at Aachen University of Technology.


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