New design tools promise to relieve setup bottlenecks by automating the documentation and validation work.
By Steve Dibartolomeo
For over 15 years, integrated circuit (IC) packages have been designed using mechanical CAD programs, such as AutoCAD, ProEngineer and Cadkey. These programs are good at defining the complex geometries used in the IC package, but are not good at embedding intelligence into the package regarding how the die should be placed and wirebonded.
Figure 1. a.) A 44-pin package. Creating a wirebond drawing manually for a small package is easy. b.) A 240-pin package. Software-driven wirebonding has a significant advantage here.
Most assembly engineers manually place and wire a die using either CAD software or a drafting board, pencil and ruler. The bond diagram is then either transmitted or faxed to the assembly line where the wirebond operator uses a printout to manually program the wirebonder by building a reference part; the bonding commands are recorded and played back at high speed. This approach has worked well for years because the pin counts were relatively small (14 to 48), production runs were long enough that the CAD and programming time was negligible, and wires could be checked by manual methods (Figure 1).
The manual approach ran out of steam in the late 1990s because:
- Pad and wire counts range from 200 to 600.
- Production runs are often shorter. The documentation and programming time play a significant role in time-to-market.
- Wires are so tightly spaced that manual checking is both extremely time-consuming and prone to errors. Some things cannot be checked manually at all – such as vertical spacing between wires.
- Wirebonders can now be programmed off-line but they require a “clean” CAD database to do that. Wire endpoints must be precise to a few microns, and the CAD drawing needs to sort the wires by bonding tier.
Because of the complexity of newer devices, wirebonding documentation and setup has become a serious bottleneck and significantly affects turn-around time. New software tools promise to relieve this bottleneck by automating both the documentation and validation work.
Figure 2. a.) A 44-pin package with intelligence added. b.) An intelligent die must include for each die pad the coordinates, size (by referring to a pad stack), net name and pad number.
To take advantage of this new software, both the package drawing and the die data need to have a certain amount of information embedded into them. Part of the software solution is to upgrade “dumb” die and package descriptions into “smart” ones.
What Constitutes a Smart Package or Die?
A smart package drawing has several key characteristics. Each package finger includes an area where the wire should attach. This area is associated with a finger number. If this finger is connected to a ball pad in an array style package, it has the ball's JEDEC number associated with it. Each die pad also includes an area where the wire should attach. Associated with each pad is a die pad number and a net or signal name, such as VSS, clock_50, VCCQ. In both cases, the die and package drawing should be centered around 0,0 and should be drawn at 1:1 scale (Figures 2a and 2b).
Figure 3. The GDSII import routine recognizes die pads by their size, aspect ratio and other attributes. For irregular shaped die pads, it uses the center of the bounding box.
When using smart packages and die, an assembly engineer is able to place and bond a 400-pin die into an existing package in a few minutes, instead of a few hours. An analysis on the wires reports any violations of wire length, angle or spacing, and violations can be corrected before hitting the factory floor. Additionally, an assembly engineer can automatically generate the bond wire drawing. The same CAD file can be loaded into the wirebonder's off-line programming software so that the wirebonder can be programmed without losing production time.
During the past 15 years, thousands of lead frame packages have been designed that were not drawn with the data needed to automatically wirebond them. Contract assemblers have hundreds of existing package designs in inventory but do not have the time to go back and redraw each one to incorporate intelligent information. Many of these designs were not generated in-house, but rather by subcontractors.
An analysis of hundreds of existing drawings has suggested a course of action for smartening them up. In general, one should:
- Check to make sure they were drawn 1:1 scale. If not, rescale to 1:1.
- Identify the units of the drawing (millimeters or inches).
- Check to make sure the package center is at 0,0. If not, re-center it.
- Draw a simple polygon defining the die attach area (paddle). This can be used later to place downbonds.
- Identify and number the wire attach point for each finger.
- If the paddle is bondable, isolate the paddle outline onto its own layer.
Steps 1, 2, 3, 4 are 6 are best done manually and can be done in a minute by an experienced CAD operator. Step 5 can potentially take hours, especially on packages with 200 or more pins.
Figure 4. A connection list can be used to force die pads to the paddle and package fingers to the paddle.
To automate step 5, one can use a proprietary program called Tagger that identifies the finger attach points and numbers them. Most parts can be tagged in one or two minutes and tagging software enables a package manufacturer or user to smarten up hundreds of existing package drawings in a couple of days. Once a package drawing has been tagged, it can be used over and over again.
If you are going to automatically bond the die using software, the die must also be “smart.” Creating a smart die depends primarily on how the raw die information is transferred to the assembly engineer.
GDSII Stream File: This is the same file used to make the IC masks. It is possible to get the layer that defines the pad openings in the passivation layer and to derive the pad centers. Generally, there is no numbering or netlist information available from GDSII.
Die Netlist: This is a spreadsheet or ASCII file that lists each pad's number, coordinates and net name.
DWG or DXF File: Occasionally, the file is already in AutoCAD's DWG or DXF format; this may include numbering or net names.
Figure 5. Wires of different length have different loop heights and are bonded during separate “passes” of the wirebonder.
Print or Plot: Sometimes, only a print or plot of the pad openings is available. In these cases, designers are expected to literally paste this onto a print of the package and use a pencil to connect the dots. Software is not designed to deal with printed, plotted or faxed die layouts.
GDSII is the mask data used to produce the chip. If possible, the chip designer should extract only the layer that defines the pad openings. Otherwise, the GDSII file may be hundreds of MB in size and very difficult to use. The GDSII import program reads the GDSII file, extracts polygons on the pad opening layer, and identifies each pad and its center even if the pad is not square or if there are different sized pads on the die.
The import module also draws the scribe line around the chip, centers a chip whose coordinates are not already centered and scales the chip size up or down as specified by the assembly engineer. It then proceeds to create a die netlist that numbers each pad, defines the center (and size) and assigns a net name to each pad.
Many times, the chip designer can supply a die netlist in ASCII or spreadsheet format. The only information the assembly engineer needs to add are the units of the coordinates (typically microns) and the width and length of the die outline. The die netlist does not need to be sorted in any way; the wirebond program will re-sort the pads during the bonding process.
Controlling the Wirebonding Process
Once a smart package and a smart die have been obtained, an engineer will want to place the die into the package and bond it up. Some directions must be given to the bonding software. Depending on the designer's requirements, there are different modes available:
AutoBond: Allows the wirebond program to decide which die pads go to which fingers based on assembly rules (i.e., the wires out should go out as directly as possible to the finger, no wires should cross and no wires should be too close together).
Connection List: Defines exactly which die pads go to which package fingers. In this case, the assembly engineer provides a list to the program – mapping each die pad to each finger (Figures 4).
Net Rules: Some die pad destinations are fixed; others are free to bond where possible. This is often the case when die input/output nets go to fingers, and power and ground nets go to rings on the package.
Organizing Wires into Bonding Tiers
When all of the wires in a package are approximately the same length, they can be automatically bonded in a single pass of the machine. High-pin-count packages often use staggered fingers or fingers on different levels (or tiers) in order to jam more fingers into limited space. This requires wires of significantly different lengths (Figure 5).
When wirebonding a dense package, the wirebonder often has to make multiple passes – first a pass for the shorter wires and then a second pass with different parameters for the longer wires. Newer wirebonders can be programmed directly from the AutoCAD file using a PC, instead of directly on the wirebonder.
Figure 6. The design rule check module flags any wire violations in length, angle and spacing.
Most assembly contractors want to take advantage of this off-line programming feature (OLP) because it is faster, less prone to mistakes and does not take a production machine off line. OLP is only possible if the wires have been sorted by pass; the designer must move all of the short wires onto their own layer. For a 300- to 400-pin package, this is time consuming – the wirebond software uses a sophisticated algorithm to do this automatically in a few seconds.
Checking the Results
Modern high-speed wirebonders work only when the wire from die to package finger follows certain constraints. Depending on the machine and the package style:
- The wire cannot be too short (typically, 1,000 µm is the shortest wire allowed).
- The wire cannot be too long (typically, 4,000 to 5,000 µm is the maximum length).
- The angle between the wire and the edge of the chip should fall in the range 0 to 45 degrees. Certain package types have an even narrower window.
- Minimum spacing between wires should be 1 wire diameter (25 to 30 µm).
For small packages, these constraints can be checked by direct examination of the bond wire drawing. As pad counts go over 200, visual inspection is time-consuming and error-prone; a software solution is preferred. After the wirebond module has placed all of the wires, the design rule check (DRC) module runs. This program checks each wire for length, angle and spacing to the other wires. Any violations are reported both on the screen with markers and to a text file. The DRC module can check 400 wires in 1 to 2 minutes (Figure 6).
Extracting a Netlist
Once the wirebond module has completed its task, the designer often needs to extract a netlist and provide it to the circuit designer. The netlist is a simple table that matches each signal net with the package's pin or JEDEC ball. The wirebond module does this by starting at the die pad and working its way along the wire to the package finger.
Even the process of entering the title border, part numbers and annotations can be sped up. A template of the title border is used and a variable takes the place of the actual value (such as longest wire length). During the documentation step, the wirebond module scans the template and presents the user with the variables. The designer fills in the correct values and the software automatically updates the title border, replacing the variable with the actual value.
Taking advantage of software to create wirebond drawings can reduce an 8-hour job to 10 minutes. The resulting data is optimized for new off-line programmable wirebonders . Because the drawing is smart, additional information, such as a netlist, can be extracted from the drawing data directly.
STEVE DiBARTOLOMEO, applications engineer, can be contacted at Artwork Conversion Software, 417 Ingalls Street, Santa Cruz, CA 95060; 831-426-6163; Fax: 831-426-2824; E-mail: email@example.com.