Incorporating cleaning into the manufacturing process can increase throughput, performance and yield
BY MICHAEL TODD AND MIKE BIXENMAN
With the trend toward smaller assemblies and faster production runs, semiconductor manufacturers clearly need help with regard to cleaning methods. The possibility of a no-clean system sounds advantageous when even the smallest contaminant can ruin a chip or printed circuit board. Of course, cleaning itself can damage flip-chip assemblies; the answer is not merely cleaning, but cleaning within best practices.
While many semiconductor manufacturers are understandably eager to adopt “no-clean” manufacturing techniques, they should nonetheless retain a cleaning step in their process for some products. It may seem counterintuitive to need to clean “no-clean” materials (after all, the phrase offers hope that we can remove, or at least minimize, the cleaning process in a production line) but recent experiments have provided evidence to support the need for cleaning no-clean materials. Specifically, flip-chip semiconductor companies can increase throughput, yield and performance if they integrate cleaning into their manufacturing process, even when they use no-clean flux.
This article evaluates the effects of post-reflow flux cleaning processes on the performance of flip-chip assemblies, with a goal toward helping to define optimal flux cleaning process parameters for high-performance flip-chip manufacturing processes. In this study, model flip-chip components were assembled, cleaned, tested and evaluated. Side-by-side comparisons of the cleaning ingredients also were conducted of three commercial no-clean flux formulations and two cleaning solvent chemistries.
Reliability is one of the chief issues for semiconductor manufacturers when selecting a soldered flip-chip interconnection system. Both mechanical fatigue and corrosion of the solder joint can significantly affect the performance of a solder-based interconnect system during service. The relative kinetics of damage accumulation because of these phenomena are influenced by the solder composition, the substrate and underfill materials, and the severity of the environmental exposure.1
Table 1. No-clean flux materials under evaluation.
Reliability also becomes a concern during service, when ambient temperature fluctuations result in differential thermal expansion between the various components of a flip-chip assembly. The expansion mismatch between these components imposes strains that produce mechanical stresses at the solder joint and die surface. These stresses are the driving force for damage mechanisms, such as crack growth and interfacial delamination. The magnitude of the stresses is determined by the assembly stiffness and the inelastic deformation properties of the solder joint. The rate of the damage process is influenced by stress, temperature and environment.1
Figure 1. 35 x 35-mm array flip-chip package with several 6.4-mm square die.
One way to improve the reliability of flip-chip interconnect systems is to use underfills. Underfill materials fill the gap between the chip and substrate around the solder joints, reducing the mechanical stresses imposed on the solder joint. High adhesion of the underfill material to the substrate and die is necessary to improve the reliability of the interconnect system.1
Unfortunately, other variables can wreak havoc on the underfill. Organic flux residues deposited onto the surfaces of flip-chip assemblies during reflow soldering operations can affect the adhesive properties of underfill materials.1 Results of thermal cycle tests and humidity storage show that the reliability of flip-chip packages is reduced by flux/underfill incompatibility.2
Table 2. Comparison of controlled cleaning processes.
While cleaning certainly can help, it can also hurt if done improperly. Flux removal techniques are used in many electronics manufacturing and assembly processes to ensure consistent materials properties and improve product reliability. These cleaning techniques typically provide clean bonding surfaces for enhanced device reliability.3 In some cases, however, cleaning techniques used in flip-chip assembly processes result in a degradation of properties, including inconsistent underfill flow patterns, the generation of voids during underfill cure and poor interfacial bond strengths.
Figure 2. Process flow of a centrifugal cleaning system.
Several aspects of flip-chip flux cleaning processes have been shown to affect the performance of flip-chip underfill materials.4
Flux residue chemistry: Flux residues may interfere with the flow of underfill encapsulants, causing gross solder voids and premature failure of the solder connection. Flux residues may chemically react with the underfill polymer, causing a change in its mechanical and thermal properties.
Cleaning solution chemistry: Cleaning chemistry left under the die as a result of the inability to properly rinse will likewise interfere with the flow of underfill encapsulants, which may cause gross solder voids and premature failure of the solder connection.
Figure 3. Effects of various cleaning processes on flow performance of underfill.
Cleaning solution application technique and process parameters: Flip-chip die have a tight pitch, low standoff and dense array of solder bumps, which make post-reflow cleaning of flux residues increasing difficult. Four key cleaning variables (cleaning solution chemistry, time, temperature and impingement energy) must be understood to achieve a robust cleaning process.
Rinse solution chemistry: A rinse medium must be soluble with the cleaning solution. Moisture left under die can affect thermal fatigue failures.
A fairly common test assembly consisting of a 35 x 35-mm FR4 laminate substrate with 16 flip-chip component sites was chosen (Figure 1). The substrate was 0.34-mm thick laminate with liquid photoimagable soldermask-defined gold-plated conductor pads. The flip-chip components used in the study were silicon nitride passivated die. These components have 48 peripheral eutectic solder bumps at a 0.46-mm pitch.
Figure 4. Acoustic microscopy images of control samples (no flux).
The flip-chip die were assembled using no-clean flux formulations, cleaned under a variety of conditions and encapsulated using a commercial epoxy-based underfill material. These assemblies were evaluated for underfill flow defects, including the presence of voids, filler striations and inhomogeneous contamination. The assemblies were then subjected to JEDEC level-three preconditioning and pressure-cooker exposure and evaluated for performance defects, such as underfill delamination and cracking. Finally, the assemblies were subjected to pressure-cooker accelerated testing (121°C, 100-percent relative humidity, 2.2 atmospheres of pressure) for 48 hours and evaluated for performance defects, such as underfill delamination and cracking.
Three commercial no-clean flux formulations and two cleaning solvents were evaluated. These cleaning processes were compared to control units that were not cleaned. The test components were assembled using a controlled process. FB250 die were first placed bumps-down into a 0.0015-in. thick bed of flux to deposit a controlled amount of liquid flux onto each solder bump. The die was placed onto the substrate and reflow soldered using a five-zone reflow furnace with a peak temperature of 230°C. Two sets of soldered assemblies were set aside as control units. Each of the remaining soldered assemblies were cleaned using the chemistries selected from phase one of the evaluation.
Figure 5. Acoustic microscopy images of samples using Flux A.
The centrifugal cleaning system used in this study consisted of a cleaning chamber, solvent reservoir, robot heat and microprocessor control system. The flip-chip test assemblies were mounted to the robot head using a fixture. The head automatically lowered the assemblies into the cleaning chamber and sealed the chamber from the surrounding atmosphere. The cleaning solution was automatically pumped from the storage reservoir into the cleaning chamber, submerging the cassette. A microprocessor executed a program that rotates the assemblies in the solution. The flip chips rotated in one direction first, then reverse and rotated in the opposite direction. This rotation-reversal action continues for the duration of the wash interval. Following the wash interval, the cleaning solution returned to the reservoir and a rinse interval began.
With the cleaning chamber still sealed, deionized water was sprayed across the flip-chip assemblies. The centrifugal action allowed the rinse water to penetrate under the die. After the rinse interval, the flip-chip assemblies continued to rotate while hot air was introduced to speed the drying process (Figure 2).
After cleaning, the test assemblies were warmed to 90°C and underfilled. The high-performance underfill used was an epoxy-based, low-stress underfill material for use on semi-rigid and flexible substrate materials with component gaps as low as 20 µm. The underfill was cured for 30 minutes at 165°C in a forced-air oven and then evaluated for evidence of flow-induced voids, filler striations and incomplete fillets by acoustic microscopy.
Figure 6. Acoustic microscopy images of samples using Flux B.
The parts were then subjected to JEDEC level-three preconditioning, consisting of unbiased environmental soak for 192 hours at 30°C and 60 percent RH followed by three passes through a reflow process with a peak temperature of 240°C ±5°C. The assemblies were again evaluated by acoustic microscopy for evidence of delamination and cracks.
Finally, the parts were subjected to pressure-cooker accelerated testing at 121°C, 100 percent RH and 2.2 atmospheres of pressure for 48 hours. The assemblies were again evaluated by acoustic microscopy for evidence of delamination and cracks.
Table 3 summarizes the test results of this investigation. Acoustic microscopy analysis of the flip-chip samples showed minimal evidence of delamination, cracking or voids created as a result of the JEDEC level-three preconditioning process. This segment of the evaluation, therefore, created negligible differentiation in performance between the control samples contaminated with flux residue and those treated with each of the cleaning processes. Acoustic microscopy analysis of the flip-chip assemblies after 48-hour exposure to pressure-cooker conditions, however, show dramatic stress-related delamination at the die-to-underfill interface.
Control flip-chip devices assembled using no flux contained neither underfill-flow-induced failures nor environmental-stress-related failures. None of the cleaning processes adversely affected the performance of these control (no-flux) flip-chip assemblies.
Flip-chip devices assembled using Flux A also contained neither underfill-flow-induced failures nor environmental-stress-related failures. Cleaning processes 1 and 2 did not adversely affect the performance of these flip-chip assemblies. Flip-chip devices assembled using Flux B contained no underfill-flow-induced striations or voids. However, this flux residue caused environmental-stress-related delamination failures after JEDEC level-three preconditioning and exposure to 48-hour pressure-cooker conditions. Cleaning process 1 eliminated the environmental-stress-related delamination failures. Cleaning process 2 improved the performance of these assemblies through environmental stress testing, but did not completely eliminate all signs of delamination.
Flip-chip devices assembled using Flux C contained both underfill-flow-induced striations as well as environmental-stress-related delamination failures. Cleaning processes 1 and 2 eliminated the underfill flow striations. Each of the cleaning processes dramatically improved the performance of these devices through environmental stress testing. However, none of the evaluated cleaning processes completely eliminated the underfill-to-device delamination after environmental stress testing.
Figure 7. Acoustic microscopy images of samples using Flux C.
Figure 4 illustrates the effects of various cleaning processes on the flow performance of the underfill material on the flip-chip test devices. Die 1 is an acoustic microscopy image of a sample flip-chip device assembled using Flux C without the use of cleaning processes. This figure shows distinct flow striations along the dispense edge of the die. These striations in the underfill material represent density variations caused by irregular flow rates beneath the die. Die 2 is an acoustic microscopy image of a similar flip-chip device assembled using Flux C and cleaned using Cleaning process 1 before the underfill process. This image exhibits only slight density variations, indicating a marked improvement over the sample without the cleaning process.
Figures 5 through 7 show acoustic microscopy images of the flip-chip test devices for each material combination from initial evaluations after the underfilling operation through each of the environmental stress tests. These images are typical for the set of images gathered for each condition. Bright white areas of the acoustic microscopy images represent areas of delamination or voids. Dark black spots along the edges of each of these images are the peripheral solder bumps.
Test data indicates that flux residues under flip-chip die may affect the flow of underfill materials, resulting in striations and voids. Furthermore, if subjected to severe environmental conditioning, flux-contaminated flip-chip devices may prematurely fail as a result of interfacial delamination. Control flip-chip devices assembled using no flux showed no signs of voids, striations or delamination after environmental testing. Likewise, test devices assembled using Flux A showed no indications of voids, striations or delamination after environmental testing. Test devices assembled using Flux B and Flux C, however, contained flow-induced failures including voids and severe striations, as well as environmental-stress-related delamination failures.
Flux A provided the most robust flip-chip assembly for the test conditions evaluated. Flux A has very low solids, which results in a low residual contamination beneath the die. One might ask, “Why not select Flux A or use no flux in the assembly of these devices to maximize performance?” The answer: The soldering assembly yields and solder joint integrity rely on the activity of the flux. Flux A has lower “fluxing” activity than the other fluxes evaluated. In some cases, this flux may provide inadequate fluxing activity to create high-performance solder joints.
Both Flux B and Flux C are high-activity fluxes that leave behind higher levels of residue than Flux A. As a result, there are voids, flow striations and delamination on control samples in which no cleaning was performed. Cleaning processes 1 and 2 improved the underfill flow performance and flip-chip mechanical stability of test devices assembled using Flux B and Flux C without causing negative effects to these devices. These cleaning processes appear to provide ideal surfaces after cleaning for optimal underfill performance beneath a soldered flip-chip device.
Cleaning processes 1 and 2 consistently provided a good surface for bonding. These cleaning processes removed enough residues from Fluxes A and B to provide good reliability through JEDEC level-three preconditioning and 48-hour PCT exposure. Furthermore, these cleaning processes did not degrade the performance of the devices in any way. Further investigation of the chemistries and processes used in these cleaning procedures will proceed to develop optimal processes for other flux/underfill combinations.
The results in favor of cleaning are a bit surprising, given the trend toward no-clean manufacturing. But, as the industry evaluates no-clean fluxes and other advances in flip-chip assembly, it is evident that cleaning still has a place in semiconductor manufacturing. AP
The authors would like to thank Kathy Costello (Dexter Electronic Materials) and Erik Miller (Kyzen Corp.) for their contributions to this investigation.
- John H. Lau, Flip Chip Technologies, McGraw Hill, 1995.
- Frank Feustel and Andrea Eckerbracht, “Influence of Flux Selection and Underfill Selection on the Reliability of Flip-Chips on FR4,” Proceedings of the 49th Electronic Components and Technology Conference, 1999.
- R. Shukla, V. Murali and A. Bhansali, “Flip-Chip CPU Package Technology at Intel: A Technology and Manufacturing Overview,” Proceedings of the 49th Electronic Components and Technology Conference, 1999.
- V. K. Nagesh, et al., “Challenges of Flip-Chip on Organic Substrate Assembly Technology,” Proceedings of the 49th Electronic Components and Technology Conferences, 1999.
MICHAEL TODD, research associate, can be contacted at Dexter Electronic Materials, 15051 E. Don Julian Road, Industry, CA 91746; 626-968-6511; Fax: 626-336-0526; E-mail: firstname.lastname@example.org. MIKE BIXENMAN, chief technology officer, can be contacted at Kyzen Corp., 430 Harding Drive, Nashville, TN 37211; 615-831-0888; Fax: 615-831-0889; E-mail: email@example.com.