The back-end process: Step 7 – Solder bumping step by step

By Deborah S. Patterson

Click here to enlarge image

Wafer bumping is replacing wire bonding as the interconnection of choice for a growing number of components. The broad term “wafer bumping” will be defined in this article as the process by which solder, in the form of bumps or balls, is applied to the device at the wafer level. The use of wafer bumping is driven either by performance, form factor or array interconnect requirements. The ability to properly design the device for bumping will have direct bearing on manufacturability, reliability, and cost savings from wafer fabrication through component assembly.

Merchant Bumping Foundries

Merchant bumping service providers must be able to offer technology that can accommodate a wide variety of wafer materials and configurations. This includes the ability to bump:

  • Prototype, engineering and production level volumes
  • 4-, 5-, 6-, 8- and, eventually, 12-inch wafers
  • Many passivation types (silicon nitride, oxy-nitride, silicon oxide and polyimides)
  • Potentially, many wafer types (silicon, ceramic, quartz, SiGe, GaAs and InP)
  • From 3 to more than 6,000 bumps per die
  • Perimeter and array patterns of varying bump densities
  • Probed wafers.

The bumping foundry must have sufficient expertise to work with the integrated device manufacturer (IDM) to help determine the optimal technology for a given device and application. Experience in the failure analysis of assembled flip chips is important because failures can occur for reasons beyond the control of the bump supplier.

Typical Structures for Flip Chips and WLPs

Historically, flip chip connoted the use of small solder bumps, typically measuring 75 to 130 µm. The new wafer-level package (WLP) technology uses larger solder balls, typically measuring 300 to 500 µm in diameter. Solder bumped flip chips typically use solder spheres to connect the device directly to the circuit board. The solder bumps are placed on the active side of the device, either directly on I/O pads or routed from them. The flip chip often requires the addition of an underfill to increase the reliability of the structure. Wafer-level packages, like flip chips, also support electrical or thermal interconnections and are flipped onto circuit boards. However, they are intended to fit into a conventional SMT assembly process with no need for additional equipment or processing steps, such as underfilling. WLPs may incorporate features to provide additional environmental protection to the device, and they permit testing at the wafer level (or in a socket). Device burn-in is not required for the majority of current device types being packaged in WLPs, but the development of wafer-level burn-in is key for the extension of the technology to additional markets.


Figure 1. Standard flip chip array with eutectic Sn/Pb solder bumps.
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Wafer bumped products typically employ one of three fundamental structures:

  • Standard designs, in which the solder is placed directly onto the final metal bond pad (I/O) without the need for additional dielectric layers or final metal routing (Figure 1).
  • Repassivation, defined by an additional layer of dielectric material that is applied to the wafer. It serves as a stress buffer layer, a planarizing medium and a final passivation layer. This technology is used when the solder bump is larger than the final metal pad, especially when there is an insufficient thickness of final wafer passivation to buffer the circuitry beneath the bump.
  • Redistribution, defined by the addition of metal and dielectric layers onto the surface of the wafer. It serves to re-route the I/O layout into a completely new footprint (Figure 2).

WLPs tend to be designed with larger solder balls for the purpose of increasing thermal fatigue lifetime if underfills are not applied. Many WLPs also employ repassivation to planarize the wafer (Figure 3). Repassivation is also used when the final metal bond pad is smaller than the diameter of the solder ball or under bump metallurgy (UBM) structure. There are many variables to use in optimizing the design of a WLP, depending upon the cost-performance requirements. As with flip chip designs, cost is reduced when the solder ball can be placed directly onto the final metal bond pad.

Under Bump Metallurgy

The UBM serves as a platform for the solder bump as well as a metallurgic system that is specifically designed to connect the wafer metallurgy to the solder bump metallurgy. The goal of this “system” is to produce a highly reliable and stable structure. The UBM overlaps the wafer passivation layer to protect the wafer circuitry from corrosion, and it should also provide the following features or capabilities:

  • Excellent adhesion to a variety of wafer passivation and final metals.
  • Low ohmic contact to the final metal bond pad. One of the first steps in the wafer bumping process is to remove the aluminum oxide from the final metal pads by a plasma back sputter or by a chemical etch. If oxides remain on the pads because of incomplete oxide removal, an increase in contact resistance will occur; an increase can also occur if the wafer fab does not properly remove the residual passivation from the bond pad, making root cause of high contact resistance difficult to determine.
  • A robust solder diffusion barrier to guarantee that the bump metals and bond pad metals do not react with each other to degrade the reliability of the system.
  • A final metal layer that ensures good solder wettability with the solder alloy.
  • Minimal processing stress to the wafer. Some wafer bumping technologies can induce too much stress on the wafer during processing, and fractures or cratering within the wafer can result. Bump shear is an excellent test to determine if the bumping process is causing excessive stress to the wafer. The bump should always shear in the solder and should not cause cratering or UBM delamination.
  • The ability to be used on probed bond pads, allowing fabs to verify their process without waiting for the return of bumped wafers.
  • Compatibility with the dielectric material used.

Solder Bump/Ball

The solder bump or ball serves as the interconnection point between device and board. If the system is designed properly, failure will occur within the solder as predicted by known reliability models. It is not unusual for underfilled solder bumps to survive well beyond other components on the board. The solder joint must provide the following features and capabilities:

  • Fully reflowable solder bumps or balls, allowing all of the solder to be placed on the device, thereby eliminating the expense of applying solder to the board for flip chips. When fully reflowed, the solder will self-center and collapse, making assembly less difficult and enhancing the reliability of the joint.
  • Well-controlled alloy composition. A variation of 10 to 15 percent of the nominal 63Sn/Pb composition can increase the liquidus temperature to 200 – 210°C. With a eutectic Sn/Pb reflow cycle, these bumps do not often wet to the bond pad.1
  • The ability to accommodate various alloy types. Eutectic Sn/Pb, high Pb, and Pb-free alloys each address distinct market requirements and supply different technical advantages.
  • The ability to control bump heights to ensure high assembly yields. A well-controlled bumping process will provide bump heights with a standard deviation less than 2.5 µm within the die and across the lot.
  • Special features, such as low-alpha emission and non-collapsible bumps, to address the needs of specific applications.

Dielectric Layers and Metal Routing

Dielectric layers are used to repassivate wafers and to redistribute the I/O pattern. Repassivation planarizes the device, provides a stress buffer layer, and protects IC metal from the UBM etch process if the device passivation contains pin holes.


Figure 2. Example of a redistributed footprint showing the original wire bond I/O pads, now routed through solder balls located in the center of the device. This flash memory device has now been turned into a wafer-level package.
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A redistribution layer can route a tight wire bond perimeter pitch to a coarser array pattern that is suitable for bumps. For flip chip devices, redistribution is used primarily to demonstrate technology feasibility. Once a flip chip version of an application has been demonstrated, the decision to redesign the devices for bumping is typically made.

For WLPs, it is common to use redistribution to provide another package option for a given IC design. The same chip can then be offered in standard wire bond packages or as a WLP. Redistributed WLPs effectively decouple the device from the package, and this enables the development of common footprints. In addition, redistribution also decouples die shrinks from the footprint and, if the device is still large enough, allows board design to remain unchanged. Wafer-level dielectric materials should possess the following features and capabilities:

  • Processing temperatures compatible with IC technology
  • Protect the device and redistribution wiring from corrosion
  • Chemical resistance
  • Good adhesion characteristics and compatibility with different passivation types
  • Low dielectric constant
  • Suitable thickness
  • Routability (support of fine lines, spaces and small vias).

Future Considerations

As in any advanced packaging scenario, the bumping manufacturer must provide a continuous source of new technology to meet the requirements of next-generation flip chip and WLP applications.

Pitch: Flip chip bump pitches will not migrate below 150 µm in the near future. Similarly, wafer-level packages at a pitch of 0.5 mm moved into production last year and will remain at this level for the near term. It is important

that new flip chip and WLP technologies can demonstrate the same pitch trends and can address future pitch roadmap requirements.


Figure 3. Cross sections of optional one-layer and two-layer WLPs with “bump on I/O” designs. The structure of the package can be modified to address electrical and reliability concerns based upon the component requirements.
Click here to enlarge image

Scalability: The ability to scale the bumping process to 300-mm wafers and beyond will be driven by both device performance and cost requirements. Solder paste deposition technology has already been shown to successfully bump 300-mm wafers. The equipment set and associated process development for plated bumping technologies must be able to control the alloy concentrations and bump height uniformity across 300-mm wafers as well.

Alloys: The bump technology must accommodate various alloys to support the demands of a diverse number of applications. Although eutectic Sn/Pb and high Pb alloys are the most prevalent bump materials used today, several new alloys are being introduced to the market. Production ready Pb-free systems are currently available from a few bumping providers. Figure 4 shows a close-up of a 250-µm full array bump pattern with Sn/Ag/Cu bumps. Reliability studies have shown that the bumped Sn/Ag/Cu alloy system results in significantly improved reliability as compared to binary Sn/Ag alloy. Alloys with very low alpha particle emissions (from 0.02 to 0.002 alpha counts/hr/cm2) are also in production today. These alloys can be processed as Pb-based or Pb-free materials depending upon the demands of the application. Other custom features, such as non-collapsible bumps or flux-less alloy systems to support RF and optical requirements are also being targeted.


Figure 4. SEM image of lead-free solder bumps. The Sn/Ag/Cu alloy is in production at Kulicke & Soffa's Flip Chip Division.
Click here to enlarge image

Dielectric materials: The migration to tighter lines and spaces and smaller vias for multi-layer build-up capability will be driven by electrical requirements and cost considerations. The option of integrating a new final metal layer as part of the bump process opens the door to creative design options. Polymer materials that will reliably support solder bumps on their top surfaces are desirable in order to reduce self-capacitance and increase routing options.

Copper and low-k dielectric compatibility: Bump structures and additional post-wafer processing techniques are being developed to accommodate copper final metal bond pads as well as the low-k inner layer dielectric (ILD) materials that make up the structure of current leading-edge (and future mainstream) ICs. Wafer bumping technology will need to maintain existing reliability requirements for solder fatigue, electromigration, thermomigration, corrosion and intermetallic formation without incurring excessive ILD stresses.

Au final metal and compound semiconductors: The next generation of millimeter-wave and optoelectronic applications will require low impedance, short electrical path lengths, excellent coplanarity and joint height repeatability. In addition, many of these systems will require a flux-less interconnect technology. These applications will be fueled by GaAs, SiGe and InP technologies. Bump structures must accommodate Au final metal bond pads and provide for adequate solder diffusion barriers. Electrical characterization of bump structures, metal traces and dielectrics will be required to complement modeling of the larger system.

Summary

Solder wafer bumping is a packaging approach that offers many options to the IDM and system integrator. It provides a robust and functional interconnect solution that preserves high performance operation. It is also an enabling solution for the ultimate miniaturization of components. As new applications continue to be defined, solder wafer bumping is emerging as a mainstream solution to advanced packaging requirements.

Reference

  1. P. Elenius, “Flip Chip Bumping for IC Packaging Contractors,” March 1998, K&S Flip Chip Division website (http://www.flipchip.com).


Designing for Wafer Bumping – IC Considerations

Once the material considerations are understood, the designer can more effectively pursue the right packaging approach for the device and application. The following checklist can help facilitate the effort.

Wafer Material

  • Silicon (Si): Well-served by all merchant bumping foundries.
  • Silicon germanium (SiGe): Compatible with silicon bumping foundries.
  • Quartz: A difficult material to handle because of equipment specific recognition issues.
  • Gallium arsenide (GaAs): A compound semiconductor that can be doped by silicon. It is recommended that the effects of processing cross-contamination are verified if GaAs processing is not separated from Si processing in the fab.
  • Indium phosphide (InP): A compound semiconductor that can be doped by silicon. As for GaAs, cross-contamination is a potential issue.

Wafer Diameter

6- and 8-inch wafer capability is more prevalent than 4- and 5-inch wafer capability. 3-inch wafers (InP) present processing difficulties outside of a university or consortia setting because high volume bumping foundries typically do not employ 3-inch equipment.

Wafer Thickness

Acceptable thickness depends upon wafer material, wafer diameter, and processing requirements. Nominal thickness should target 0.5mm for 4- to 6-inch Si wafers and 0.6 mm for 8-inch Si wafers. Backgrinding can create stress risers that may impact wafer yields during the bumping operation. A chemical etch is recommended after backgrinding.

Wafer Passivation

  • Pinholes should not exist; two layers of passivation are recommended. If pinholes are present, a repassivation layer is recommended.
  • Some polyimides may not be compatible with a particular bumping process.
  • Passivation openings should be designed to be as large as possible to reduce current density and improve electromigration life times.
  • Passivation openings should be modified to support the flip chip or WLP process.
  • Passivation openings must be clear of residual oxide due to incomplete passivation opening in the IC fab.

Alloys

  • Fully reflowable alloys are encouraged.
  • Consult the bumping provider for a list of qualified alloy types for a given application (eutectic Sn/Pb, Pb-free, low alpha).
  • Ensure that alloy composition is well-controlled.
  • Understand the specifications for bump height both within a device and across the lot.
  • Understand which coplanarity procedure is being used and how measurements are defined.
  • Each alloy should be qualified by technology (direct bumping, repassivation, redistribution, etc.).

Pitch

  • Pitch capability may vary by pattern, alloy type and technology.
  • Solder alloys need to be qualified for underfilled and non-underfilled applications.
  • When underfill is omitted from the assembly process, it is recommended that the bump contain a larger volume of solder because this translates into higher bump standoff and increased reliability.

Bump Placement

  • Bumps should be placed as symmetrically as possible.
  • Dual-purpose designs can be created to support both wire bond and flip chip assembly approaches.
  • Dummy bumps can be added to certain designs.
  • Bumps need to be placed sufficiently within the area of the device so as not to interfere with the dicing operation.
  • The use of bumps over active areas will be dictated by the electrical sensitivity of the circuitry on the device.
  • Placement of the solder bump or ball on top of a polymer layer offers reduced self-capacitance, which is desirable for high-frequency applications.

Inspection and Test

  • Standard inspection should include visual sampling, bump height and bump shear testing.
  • Resistance and shear test patterns are recommended as a process monitor.
  • Full inspection and wafer mapping services can be performed as special services, typically with associated costs.
  • Wafer-level test is the preferred approach to inspecting bumped wafers.

Assembly Considerations

  • Targeted bump height and die coplanarity must be repeatable on a lot-to-lot basis.
  • Final joint heights must accommodate underfills where required.
  • Some bumping suppliers offer recommendations on compatible fluxes, underfills and assembly design rules derived through internal reliability testing.

Deborah Patterson is Director, Market Development and Strategic Applications at Kulicke and Soffa Flip Chip Division, 3701 E. University Drive, Phoenix, AZ 85034: 602-431-6020 x212; Fax: 602-431-6021; E-mail: Dpatterson@flipchip.com.

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