Texas Instruments offers world's smallest logic devices
Dallas – Though Toshiba once had the smallest logic device in a two-billion unit market ($400 to 500 million), Texas Instruments (TI) has taken the competitive lead by introducing the NanoStar Little Logic – the smallest single-gate logic family available. Nano- Star consists of single-gate logic functions packaged in a chip scale package (CSP). The product reduces board space requirements several times over the conventional 5-pin package, and is driven by the demand for applications requiring a very small mounting area. The Little Logic family offers the most popular logic functions for space-constrained systems, such as cellular phones, pagers and portable consumer products.

Little Logic can also be used as glue/ repair logic to implement last-minute design changes or to eliminate dependence on intricate line layout patterns and simplify routing.

The product measures 0.5-mm high with a 1.4 x 0.9-mm footprint. This is a 70-percent reduction in size from TI's SC-70 (DCK) logic package and a 13-percent decrease in size from any other logic package solution in the market, according to TI.

TI’s chip scale package (dimensions in mm).
Click here to enlarge image

NanoStar packaging will first be introduced in a 5-pin, single-gate, low-voltage CMOS (LVC) technology. LVC dual-gate devices will follow in an 8-pin version. The devices operate at 1.8 V, and are optimized at 3.3 V, providing low power consumption and medium current drive capability. These devices will allow designers to place more functions in a tighter space, while improving system performance.

Additionally, TI says that NanoStar offers better thermal and electrical properties than previous TI devices, and the self-planarizing eutectic solder balls allow minimal positional tolerance when placing the devices on the board, thus enhancing manufacturability. Board-level reliability data indicates 1,150 cycles to 1.0-percent failure.

TI is also working toward eliminating the lead in its logic devices to conform to recent lead-free initiatives. The first products in NanoStar packaging are sampling now, with volume production scheduled for the fourth quarter of 2001.

LSI Logic answers call for high signal I/O density
MILPITAS, CALIF. – LSI Logic Corp. has announced the flxI/O flip chip for high-performance products in the communications market. flxI/O is LSI's third generation of organic flip chip packaging products, offering ASIC/SOC designers improvements in signal I/O density, electrical performance and a significant reduction in die size, when compared to a peripheral I/O package.

flxI/O flip chip uses an area array approach to signal I/O placement, resulting in optimal die sizing and increased signal I/O count compared to peripheral schemes. Rather than restricting signal I/Os to the periphery of the die, flxI/O allows signal I/O placement anywhere on the die, giving designers the flexibility to realize up to 60 percent die size reduction or increased signal I/O density up to 65 percent.

“Communications devices are demanding greater signal density and performance,” said Stan Mihelcic, manager of advanced packaging solutions, technology marketing, at LSI. “flxI/O flip chip package technology is better able to meet the demanding performance needs of the advanced chip designs than wire bond or ceramic packages.”

The construction of flxI/O flip chip is the same as FPBGA-HP and FPBGA-4L, making it optimal for high-volume assembly.
Click here to enlarge image

flxI/O uses an organic substrate material similar to that used by the FPBGA package family. The use of an organic substrate offers greater signal density and improved electrical performance, as well as enhanced solder ball interconnect reliability. flxI/O flip chip features include signal I/O counts up to 1,600, 100-percent differential signaling or single-ended I/Os, up to 12 voltage splits, enhanced thermal performance, efficient PWB escape routing, and a complete designed generic package family.

Standard packages are available in high volumes in body sizes from 31 mm to 50 mm/side, with ball counts from 896 to 2397. Chip designers can also benefit from the automated package tools for flxI/O packages within the FlexStream tools suit, which integrates LSI Logic tools with third-party EDA tools, creating a complete system-to-silicon design environment.

STATS provides thermal simulation worldwide
SINGAPORE AND MILPITAS, CALIF. – ST Assembly Test Services Ltd. has recently expanded its Simplified Package Modeling (SPM) services to customers in Europe and Asia. SPM offers a unique approach to thermal simulation; rather than waiting for completion of the final substrate or lead frame design, SPM can occur as soon as a customer identifies the basic package design requirements, such as package type, die size, number of solder balls and copper layer count.

As demand for complex, non-symmetrical, stacked die and other multi-chip packages continues to grow, conventional simulation techniques are limited to a small symmetrical section of the package itself and other elements such as the underlying PCB and heat sinks. Keith Bailey, package characterization engineer for STATS, points out that there is a distinct advantage in SPM's ability to model an entire cube within JEDEC standards, rather than cutting the package into fourths or eighths, and being forced to rely on the symmetry of the package.

“The SPM methodology delivers unparalleled advantages to our customers through cycle time reduction, increased design flexibility and a focus on complex design issues,” said Roger Emigh, manager of package characterization at STATS.

SPM offers a new level of capability through the combination of STATS' package design expertise, its thermal test database, and the Flomerics Flotherm simulation tool. The SPM technique creates simplifications that combine discrete elements within the package, such as traces, bond wire or lead frame fingers, into larger blocks of material. These cuboids are each then assigned an “effective” thermal conductivity that produces the correct thermal behavior during the simulation process. Other materials within the package that are thin, such as the die attach adhesive layer, are collapsed into a zero thickness layer that produces an appropriate resistance to the passage of heat. Also, the underlying PCB test board is simulated, and STATS can include any type of heat sink that may be required by the customer.

STATS reports that the SPM process gives results that are consistently accurate within five percent of the actual thermal resistance determined by subsequent testing of the final devices. This data is generally delivered to customers within one or two days from receipt of general package information.

Industry leaders support new chip architecture
SUNNYVALE, CALIF. – A group of leading companies from throughout the semiconductor industry have launched a five-year initiative aimed at accelerating the availability and fabrication of the X Architecture – a new interconnect architecture based on the pervasive use of diagonal routing. The consortium, named the X Initiative, will provide an independent source of information about the X Architecture, facilitate support and fabrication of the X Architecture through the semiconductor industry supply chain, and survey usage of the architecture to track its adoption.

The X Architecture is said to reduce the total interconnect on a chip by more than 20 percent. Based on initial evaluations, this wire-length reduction is expected to deliver more than 10 percent greater chip performance, more than 20 percent less power dissipation, and more than 30 percent more chips per wafer for complex, multiple-metal-layer ICs, such as systems on chip.

For the past 20 years, chip design has been primarily based on the Manhattan architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores, by preserving the Manhattan geometry of metal layers one through three.

Charter members of the initiative include Dai Nippon Printing, DuPont Photomasks Inc., Etec Systems Inc., KLA-Tencor Corp., Numerical Technologies Inc., PDF Solutions Inc., Simplex Solutions Inc., Tensilica Inc., Toshiba Machine Co. Ltd., Toshiba Corp., and Virtual Silicon Technology Inc. Membership is open to all companies throughout the semiconductor supply chain.

Amkor expands matrix processing and parallel testing
CHANDLER, ARIZ. – Amkor recently announced that more than half of its leadframe package assembly capacity is now processing parts in its new high-density matrix format. The concept, which Amkor executive Scott Voss describes as the equivalent of a wafer fab's shift to 300 mm wafers, is to process many more packages at a time, in a standardized 70 x 250 mm leadframe strip.

The key advantage according to Voss, Amkor's corporate VP for the leadframe products business unit, is the parallel test capability. Up to 48 parts can be tested per touchdown, and even if the tester lacks the bandwidth to test all of those parts simultaneously, the time-consuming indexing steps are reduced because of the ability to contact more devices simultaneously. Tester bandwidth and pincount capacity are actually the current limiting factors in the throughput, but it is expected that advances in tester capability will continue to drive this approach to higher pincount packages. It is currently most appropriate for low pincount packages, with 100-lead parts being the highest pincount units processed in this format. Voss also said that very high volumes are needed to justify the tooling cost of $2.5 million required for each package that is transferred to the matrix assembly and test method. Once that is in place, though, the factory output is approximately doubled.

The parallel processing approach here is something like wafer-level packaging (WLP), but instead of running wafers through the packaging flow, a large batch is created and processed all at once. The economies of scale associated with WLP apply here, but this is all taking place in the extreme high volume realm, with Amkor by itself having the capacity to process three billion units per year in this way.

FeinFocus and WABCO announce joint project
STAMFORD, CONN. – FeinFocus USA Inc. has recently announced a joint research and development project for the development of an automated three-dimensional inspection

X-ray system for microsystems between its sister company, FeinFocus Röntgen-Systeme GmbH, the Lower-Saxonian manufacturer of microfocus X-ray inspection systems, and WABCO Fahrzeugbremsen, Hannover. WABCO manufactures and sells EBS and ABS braking systems, as well as electronic control systems for the commercial vehicle industry. The cooperation is projected for three years with federal funding provided by the Lower-Saxonian Ministry of Economics, Technology and Traffic.

“The mutual benefits from such a joint venture are more than obvious,” said Joachim Gudat, FeinFocus worldwide sales director. “The beta system developed by the Garbsen company is installed at WABCO's facility and will be jointly developed further during the three-year project period. The result will be a system solution for the automatic inspection specifically in the PCB assembly industry.”

The heart of the modular and compact system is the inspection technique of oblique angle viewing, which allows for the inspection of hidden solder connections in the third dimension. A proprietary automation software program will integrate the analysis data into the production process.

After successful completion of the project, FeinFocus will manage the sales and marketing of the system. WABCO, in turn, receives a “tailor made” system solution, including all updates and add-ons as well as the complete, jointly developed software.


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