Solutions for wafer edge processing
BY MANISH RANJAN AND STEPHEN KAY
As flip chip and advanced packaging techniques achieve industry acceptance, device manufacturers are faced with several manufacturing challenges encountered during the various processes. Lithography is one of the crucial process steps that must be addressed carefully to ensure successful wafer bumping. Because of the high costs associated with defects and consequent rework, yield optimization is one of the primary factors affecting the choice of equipment. The need for yield optimization along with technical and financial advantages has resulted in the widespread acceptance of 1X stepper technology for advanced packaging lithography.
This article discusses the need for wafer edge processing solutions. Because both positive and negative resists are used in device fabrication, the edge processing solution should either be able to expose or exclude the outer edge of the wafer during the photolithography process step, depending on the type of resist used.
Lithography for Advanced Packaging
To address the needs of evolving technology, semiconductor manufacturers are applying traditional front-end lithography equipment to leading edge back-end packaging applications. This adoption has been driven by the realization that the imaging requirements of wafer bumping are subject to the same production necessities as front-end semiconductor fabrication. As a result of issues regarding yield, imaging performance, process control and cost savings, semiconductor manufacturers have largely abandoned the use of contact or proximity aligners for front-end applications. These issues have also been witnessed during the lithography required for wafer bumping and have resulted in the shift toward stepper technology for advanced packaging lithography.
1X Stepper Technology
Projection optics used by stepper technology provides several technical and financial advantages as compared to the full field exposure techniques used by contact or proximity aligners.
Figure 1. Comparison of wafer layout with and without edge processing solutions.
Imaging performance: The use of projection optics during imaging elimi-nates the need for a close wafer-to-photomask proximity. Unlike the contact or proximity aligner, the stepper resolution is not a function of the distance between the wafer and the photomask. The use of projection lithography also enables variable focus capability and provides uniform exposure over the surface of the wafer, resulting in improved CD uniformity and more consis-tent resist sidewall profiles.
Alignment performance: The use of enhanced global alignment during exposure using stepper technology provides enhanced alignment capabil-ity. In addition, imaging using stepper technology compensates for mask run-out, isotropic wafer scaling, rotation errors and orthogonality errors by adjusting the exposure locations on the wafer. Contact and proximity aligners conduct alignment on a global basis using two alignment targets and cannot compensate for mask run-out or grid errors. Unlike the quartz reticles used for imaging in stepper technology, contact aligners use sodalime photomasks. The coefficient of thermal expansion mismatch between the sodalime photomasks and the silicon wafers, coupled with the long exposure times, results in significantly degraded alignment performance. 1X systems can achieve impressive overlay performance through the use of machine vision alignment systems that uses pattern recognition to align the reticle to the wafer. This method of image capture ensures that no special alignment targets are required on the wafer. This alignment has been shown to be robust with alignment through thick films and low-contrast images.
Figure 2. Process sequence for wafer edge exposure.
Yield performance: The use of stepper technology eliminates the inci-dental wafer-to-photomask contact witnessed while imaging using con-tact aligners. Contact during imaging by contact aligners reduces the life of the photomask and introduces residual resist on the photomask, which leads to repeating damages during imaging. The use of enhanced global alignment and dynamic focus capabilities contribute to significantly bet-ter process yields by reducing the alignment errors and improving the quality of the image being exposed. The high level of process automation provided by stepper technology reduces operator interven-tion and provides a more robust process.
The Need for Wafer Edge Processing Solutions
As with any wafer fab equipment, wafers processed using stepper technology must be compatible with the next process sequence. Once the photoresist is patterned, the wafer is processed for metal deposition. One of the unique features of gold or solder plating is the edge processing requirement.
Figure 3. Process sequence for wafer edge exclusion.
A typical plating chamber-to-wafer interface requires the wafer edge to be cleared of resist material for reliable electrode contact. The current for electroplating is then injected in the seed layer to ensure homogeneous current distribution. Because both positive and negative resists are used in flip chip and wafer-level CSP fabrication processes, the edge processing solution must be compatible with both scenarios. Positive resists require the wafer edge to be exposed during lithography so that the resist is washed away from the edge after development. On the other hand, negative resists require the wafer edge to be excluded from exposure so that the edge is resist-free after development.
The features desirable for edge processing solutions are:
- The outer edge of the wafer (1.5 to 6 mm) should be resist-free for electrode contact.
- Edge exclusion/exposure needs to be adjustable in 0.1-mm increments.
- Solutions should be applicable for all standard wafer sizes (150 to 300 mm) with either flat or notched wafers.
- Edge processing must be compatible with photoresists with thickness ranging from 1 to 120 µm.
- The entire process should be automated to the maximum extent.
In the absence of an edge processing solution for steppers, small field sizes are used to ensure that the outer edge of the wafer is clear of any resist material. This affects the equipment throughput because of the reticle field change time and the increased number of exposure shots. The use of a unique edge processing solution enables high equipment throughput while imaging using stepper technology. Figure 1 compares the number of exposure shots required using the multi-field approach and the edge processing solution. It is observed that the use of an edge processing solution provides a significant reduction in the number of exposure shots and enables the use of full stepper field during exposure.
The edge exposure requirements arise when a positive resist material is used during device production. The requirements for edge exposure are addressed during the pre-alignment process sequence. The incoming wafer is mounted on the pre-aligner, and the outer edge of the wafer is cleared of any resist material by using a light source. Figure 2 shows the process sequence during photolithography to address the edge exclusion requirement. The edge exposure coverage is available in the range of 1 to 6 mm from the outer edge of the wafer. Because the edge exposure process sequence is conducted during the pre-alignment step, the equipment throughput is not affected.
The edge exclusion coverage is required for processing negative resist materials. This requirement is addressed using a mechanical ring. The ring is positioned on top of the wafer, preventing the negative resist from being exposed. This, in turn, ensures that the resist material is removed during the develop process. Figure 3 shows the process sequence during photolithography to address the edge exclusion requirements.
Figure 4. Effect of exposure shots on throughput.
The wafer is removed from the boat and placed on the pre-aligner. After the wafer is aligned, it is transferred to the chuck. If the edge exclusion option has been selected in reticle data, the stage is moved under the edge exclusion station. The edge exclusion station consists of an arm mounted on the front pedestal to pick up and drop off the edge exclusion ring. The arm is positioned over the stage and placed on the wafer before photo exposure. After completing the exposure, the wafer is returned to the cassette and the entire process sequence is repeated again. The exclusion rings are interchangeable and can be ordered to meet the various exclusion widths and configuration options.
Impact of Edge Processing on Throughput
Edge processing solutions enable the use of the full stepper field during the photolithography exposure, which eliminates the use of multiple small field sizes required for exposure. Figure 4 illustrates the effect of the number of exposure shots on the equipment throughput at various exposure doses. Figure 5 compares the throughput for an optimized stepper set-up vs. a non-optimized set-up. It is observed that the use of edge processing solutions increases the throughput performance significantly (three-fold) at higher exposure doses, typically required for advanced packaging lithography. This throughput comparison was conducted on 200-mm wafers.
The adoption of advanced packaging techniques has affected the equipment selection criterion for the associated process steps. Production considerations, such as throughput, yield, process latitude, technical capability and scalability concerns, have enabled 1X stepper technology to be effective for bump and wafer-level processing.
Figure 5. Effect of edge processing solution on equipment throughput.
Both positive and negative resists are being used in device fabrication. Therefore, there is a need for both the edge exposure and the edge exclusion solutions. The use of edge processing solutions enables the use of full field during exposure, resulting in a high equipment throughput. AP
Manish Ranjan, senior product marketing manager, and Stephen Kay, director of product marketing for packaging technology, can be contacted at Ultratech Stepper, 3050 Zanker Road, San Jose, CA 95134; 408-321-8835; Fax: 408-325-6444; E-mail: firstname.lastname@example.org and email@example.com.