Micro inspection for wafer bumping COVERSTORY Inspection requirements for wafer-level packaging processes By Steve Hiebert Driven by consumer demand for electronic products of both high performance and compact size, the number of integrated circuits (IC) being packaged in flip-chip or wafer-level schemes has increased dramatically in recent years. The demand for bumped wafers for flip chip in package (FCIP) and flip chip on board (FCOB) will increase at a compound annual growth rate of more than 35 percent through 2005, according to one report.1 As wafer bumping continues to grow, automated inspection and metrology in bumping and other wafer-level packag-ing (WLP) processes have become increasingly important. Because the design rules associated with bumping and WLP are considerably relaxed com-pared to those in front-end wafer pro-cessing, sub-micron inspection is not necessary. Defect detection and metrol-ogy measurements with sensitivity of one or more microns are generally suf-ficient. However, inspection for these applications does present a number of unique challenges. Background The process of bumping wafers for flip chip packaging emerged from IBM in the 1960s with its “controlled collapse chip connection” (C4) technology. In recent years, a number of variations to the original C4 process have materialized, allowing the cost-effectiveness of flip chip schemes to improve dramatically. Generally, these variations involve wafer-level processes where bumps of solder, gold or other material are deposited on the wafer via evaporation, stencil printing, electrochemical plating or electroless plating. Recently, WLP has been the subject of significant research and development. For a number of IC products, WLP is a logical extension of wafer-level bumping with a lower cost, in addition to further reducing the size of a packaged product. A number of dynamics are responsible for increasing the importance of automated inspection in bumping and WLP processes: New processes and materials have been introduced; several others, including redistribution and lead-free processing, are currently emerging.Bump size and pitch have been scaled down with accelerated reduction in design rules projected on the International Technology Roadmap for Semiconductors.2Demand for bumping and wafer-level packaging is resulting in the proliferation of outsourcing services – services that often leverage either newly developed or newly licensed technology. Automated inspection fulfills two critical roles in wafer bumping and wafer-level packaging: Process control and yield enhancementIncoming and outgoing quality assurance. Each of these roles can be explained in greater detail by considering a sample application. Typical Electroplated Lead/Tin Bump Process Because of its cost-effectiveness for high-volume bumping, particularly for die with high I/O counts, electroplating is emerging as a significant bump deposition process. Figure 1 depicts a typical flow for an electroplated lead/tin solder bump process with the key steps described below. Deposit UBM Material: Various metal film stacks are used as a barrier between the bond pad and the solder bump and as the electrode for electroplated deposition. The metal film stack, often referred to as under bump metallurgy (UBM), is typically sputter deposited in blanket films on the wafer. Figure 1. Typical process flow for electroplated Pb/Sn bumps.Click here to enlarge image Coat-Expose-Develop: Patterning wafers for bump loca-tion is analogous to the lithographic processes in the wafer fab. A coating of light-sensitive photoresist is applied to the wafer, regions are exposed to light using a mask or reticle, and the resist is developed such that exposed areas are stripped away leaving holes where the bumps will be located. For the representative process illustrated in Figure 1, typical values for resist thickness, pattern opening, and bump pitch are approximately 30, 100 and 200 µm respectively. However, for the most aggressive bump pitches and for some emerging bump materials, thick resists on the order of 100 µm have been introduced. Electroplate Solder Material: The bump material, typically a lead/tin solder mixture, is deposited via electrochemical plating. Plated deposition occurs only in the openings in photoresist created by the lithography process. For many processes, including that represented in Figure 1, plating continues until the bump grows beyond the confines of the resist pattern. This results in a “mushroom” shape. For thick-resist applications, the mushroom top of the bumps is much smaller than for thin resists. In some cases, the plated material may be confined completely within the photoresist. Strip Photoresist: Once the bump material has been plated on the wafer, the photoresist layer is removed. This is done with a resist strip step similar to those performed in the wafer fab. Etch UBM Layers: To electrically isolate the bumps on a die, the blanket UBM layer is etched away. The bump process must be robust against base metal undercut that occurs during this wet etch step. Reflow Bumps: When heated, surface tension causes the bumps to transform from mushroom (or pillar) shape to near spherical shape. The lead/tin solder only wets the base metal remaining following the UBM etch step. The relative height and diameter of the bump depend primarily on base metal area and the process conditions of the reflow step. Variation in this process flow persists across IC manufacturers and bump contractors. For example, while most processes reflow the bumps after UBM etch, certain bump processes have been developed where reflow precedes UBM etch.3 In addition, some companies integrate wafer probe/test after reflow while others perform this after UBM etch. There are also bump facilities with evaporation or stencil printing as the deposition method of choice. Automated Inspection for Process Control Automated inspection inserted at various points in a bump process flow provides valuable information about the health and performance of the process. Yield-impacting excursions may be quickly detected and corrective action taken promptly. Inspections incorporating integrated metrology provide even greater value by allowing key process parameter trends to be monitored. Figure 2. Inspection and metrology points for a typical electroplated bump process.Click here to enlarge image Analogous to defect monitoring and yield management strategies in the main wafer fab, bump process facilities have found value to inspec-tion at numerous points in the process flow. Figure 2 shows inspec-tion and metrology points for the representative electroplated bump process flow. After Develop Inspection: Patterning problems are identified by applying micro inspection immediately fol-lowing the develop step in the lithog- raphy area. Key defect types relate to patterning errors, such as missing resist openings, unexpected openings and bridging between adjacent holes. In addition, scumming can ultimately lead to missing or undersized bumps. Integrated metrology allows CD and overlay measurements to be made by the inspection system. One major benefit of after develop inspection (ADI) is the pos-sibility of rework when excursions are detected. In general, ADI defects are 2-D in nature; that is, they may be observed with top-down brightfield imaging schemes that do not provide much height or depth discrimination. Post-plate, Pre-strip Inspection: Inspection of wafers imme-diately after electroplated deposition is useful for ensuring that the height of deposited material is within acceptable tol-erances. If underplating is detected, rework is possible by rein- troducing the affected wafers to the electroplating system. While many defects, such as missing bumps or bridging, are detectable using 2-D inspection, height and volume defects require 3-D measurement techniques. Post-plate, Post-strip Inspection: Critical defects, such as missing bumps, high- and low-diameter bumps, and bridging, are most reliably detected immediately following resist strip due to the high contrast between as-plated solder and back-ground base metal. Such defects are readily observed with top- down 2-D imaging techniques. However, detection of critical low- and high-height bump defects, as well as accurate meas-urement of bump height and volume, requires 3-D technolo-gy. As with the pre-strip application, it is essential that the inspection system be designed to obtain 3-D data on as-plated bumps, which tend to have high surface roughness and signif-icant scattering of incident light. After UBM Etch Inspection: Automated inspection following base metal etch allows the etch process to be monitored and controlled. The key defect types are residual base metal along with the previ-ously mentioned bump defect types (missing, bridging, oversized, under-sized, etc.). Because the base metal is etched away, detection of bump defects is generally more difficult because the contrast between bumps and back-ground is reduced. Reflow Bump Inspection: Inspection following reflow is a final opportunity to identify bridging and defects relat-ing to bump geometry. In addition, measurements of bump height and die co-planarity provide immediate feed-back for process control of the reflow step. Incoming and Outgoing Quality Assurance Inspection for the purpose of incoming and outgoing quality assurance is particularly significant in wafer bump processing and wafer-level packaging because of the common exchange of in-process product from one company or location to another. Many bump or WLP lines require quantitative validation that incoming product to be processed is of good qual-ity. If there are problems with the final pad etch of the passivation layer in wafer fab, then die yield at the completion of a bump/WLP process is adversely impacted. Immediate knowledge and rapid action minimize product risk and prevent processing of unacceptable incoming material. Incoming or passivation inspection generally is a 2-D inspection, but high inspection throughput is necessary because of the desire to sample up to 100 percent of the die and I/O pads. Conclusion The importance of automated inspection in wafer bumping and wafer-level packaging will continue to increase in order to meet the needs of process control, yield enhancement, and quality assurance. Sub-micron defect detection is not critical for these processes; but there are several key inspection requirements that must be met: High Throughput: Inspection must be fast to be compatible with the growing demand for high-rate sampling or 100-per-cent inspection. 2-D and 3-D Capabilities: 2-D techniques provide valuable information for many process flows and steps. However, 3-D inspection is necessary for detecting critical defects related to bump height. 3-D inspection should be designed for accurate operation on both as-plated and reflowed bumps. Integrated Metrology: The integration of accurate 2-D and 3-D metrology provides valuable data for process control. Key parameters include bump height and diameter for plating or reflow, and CD and registration for lithography. Broad Application: For maximum utility of an inspection system, the system must be suitable for a wide range of appli-cations, including passivation, after develop, plated bump, and reflowed bump. AP References E.J. Vardaman et al., “Flip Chip Markets and Infrastructure Development,” TechSearch International Research Report, May 2001. “International Technology Roadmap for Semiconductors 2000 Update: Assembly and Packaging,” pp. 9-10, http://public.itrs.net. P.A. Magill, J.D. Mis, and G.A. Rinne, “Considerations for an Electroplated Flip Chip Process,” IMAPS Proceedings, May 1998, also available at www.unitive.com. Steve Hiebert, senior product marketing manager, can be contacted at KLA-Tencor, One Technology Drive, Milpitas, CA 95035; 408-875-0699; Fax: 408-875-2620; E-mail: email@example.com.