From air gaps, to ALD (atomic layer deposition) at room temperature, to CVD vs. SOD (spin-on dielectrics) and VICs (vertically integrated circuits) – the recent AVS Conference on Microelectronics and Interfaces was a voyage into the future.
VIC, a 3D-integration technology, is being held out as hope by Infineon Technologies’ M. Engelhardt for the manufacture of ICs several generations beyond the limits of optical lithography. The idea is to use interchip vias for electrical connections in what is essentially a wafer stack – with the top wafers being thinned and glued onto planarized bottom wafers. The technique presented by Infineon uses only CMOS-compatible processes and no wafer backside processing. Because the process uses fully processed and electrically measured/tested product wafers, overall yield may be limited by the ability to have perfect bonding of the vertical interconnects.
Another futuristic pursuit that will rely on reliable manufacturing processes is the use of either porous low-k dielectrics, or even air, coupled with Cu to minimize the RC delay of the interconnect structure (paper presented by S.V. Nitta of IBM T.J. Watson Research Center). While David Wang, president and CEO of ACM Research, thinks using air is a good idea, he hasn’t seen a viable approach published that can be implemented into semiconductor devices taking into account multi-layer structure and device reliability. “However, nothing is impossible until we try it,” says Wang.
Trikon Technologies’, Andy Noakes, CVD products marketing manager, reports that the company is betting that CVD low-k dielectrics are the right way to go rather than SOD. “CVD will beat SOD because it is lower cost and presents less risk,” states Noakes. “The industry has used CVD for years and logic manufacturers will choose CVD over SOD every time if the results are equal.” Noakes does add that SOD is extendible down to k values of about 2.0 and maybe a bit below, so the challenge for CVD is to match these results and International SEMATECH (ISMT) is addressing the issue.
ISMT Project Engineer, Jeff Lee, presented results of its evaluation of Trikon’s Orion CVD dielectric material which showed the feasibility of integrating it in single level metal Cu damascene test structures. Lee reports that the material met ISMT’s specifications for characterization at the one-level build and the organization will continue to test the material over a four to six month timetable, noting that the material needs to be optimized for etch, ash, CMP, and other processes.
Judging by the number of papers on ALD – 13 total, four more than those for the next highest categories of CMP and plasma etching – interest in this monolayer approach is growing. While ALD at temperatures above 200 degrees C has achieved some measure of being considered a manufacturable process, doing so at lower temperatures (possibly as low as room-temperature) is still being evaluated. The interest in room temperature ALD is spurred by the growing requirement to minimize thermal budgets (e.g., minimize diffusion of dopants), as well as fulfilling a need to explore applications such as deposition on plastics. Arthur Sherman, president of Sherman & Associates, also believes deposition of Cu seed layers could possibly benefit from a low temperature ALD process as a way to minimize agglomeration effects that occur even at moderate temperatures. Farther out in the future, he speculates that growing amorphous metals, which could be excellent barrier layers, could be accomplished using room-temperature ALD to prevent film crystallization.
Sherman, and others (IBM Research, UC Berkeley), have already been able to demonstrate room-temperature deposition of aluminum oxide, titanium and titanium nitride. Recently, ASM/Genitech reported preliminary data on low temperature tantalum. “I think the first commercially viable low temperature ALD process will be for high-k gate oxides, because growing a 30 angstrom film uniformly over a 300mm wafer needs an inherently very uniform process,” predicts Sherman. After that, the next application the industry might pursue is barrier films. “It won’t be possible to use sputtering to deposit layers into 10:1 aspect ratio holes,” he explained.