10 years ago in Advanced Packaging Thermal Management for Laser Diodes Evolves - In the very first issue of Advanced Packaging, thermal management was probably the biggest topic. One feature article was about the use of diamond substrates to decrease the thermal resistance between the chip and the ambient. Ten years ago, there was significant interest in the use of diamond for thermal management because of its extremely high thermal conductivity – about five times that of pure copper – but the widespread proliferation of diamond for this application never occurred. Even improved processes for depositing thin films of diamond did not make it take hold as a mainstream technology. With the current directions of technology shrinking to the molecular level, though, it would not be surprising to see diamond films emerge again as a viable option for more applications. One interesting detail of the article was the nature of the thermal modeling performed. A two-dimensional model was used to make the computations “tractable,” which would be unheard of today for a serious analysis of this kind. Some of the work would be indistinguishable from today's work, though – the authors did cite a laser diode as the type of chip for which the diamond technology would be appropriate. Wire Bond Yield Critical Then and Now - In the early 1990s, a large fraction of articles about packaging seemed to have a graph showing the overall yield of a module or chip by giving the yield and quantity of each component or bond. Advanced Packaging was no exception, with one article showing such a graph with the device yield vs. the number of bond pads for wire bond failure rates of 10 and 100 ppm. Of course, there is a dramatic difference in yield between the two cases as the number of wire bonds increases. The point was, and still is, that wire bond yield is a critical driver of the packaged device yield, especially for high pincount devices. Another article in the first issue of Advanced Packaging clarified this even further, with a breakdown of multi-chip module failures by cause. The majority of failures were caused by bad wire bonds. Yes, wire bond failures were more common than all other failure modes combined, including bad die. Wire bond testing during process development was a critical part of process development. Wire bond yields are higher today – but so are pincounts – so accurate wire bond testing continues to be an important part of any high-volume process development program. And, just in case you are curious, the leading edge wire bond pitch cited then was 4.5 mils (115 microns). Same Old Same Old - Wafer-level burn-in and test was and still is the ultimate goal to enable the effective use of bare die in electronic assemblies. The first two issues of Advanced Packaging clearly reflected the need for “known good die” (KGD). One article about testing of multi-chip modules (MCMs) stated, “The biggest challenges are die quality, test vector generation, and fault isolation and repair.” “Die quality” was listed first in the article about module testing. Die quality is still a critical issue, although the approach in 1992 focused more on just living with sub-par die yields and dealing with it at the MCM test level. Reworkability was a key feature of MCM technologies, but today the approach for many applications is to use multi-chip packaging only when the die yield is high enough that the compounded yield is still very high. Repairing an assembly is currently less appealing than just throwing out a bad unit, including any good chips that might be housed with one bad one. Another article had a round-table discussion about securing known good die, and some of the quotes could be from 2002: “Cost-effective burn-in and testing is the paramount challenge to suppliers of known good die.” Another expert said, “The challenge is to acquire die that are fully tested, to enable the supplier to guarantee data sheet specifications, and already burned-in to alleviate infant mortality rates.” Two others are quoted as saying, “The major challenge is to achieve die quality equal to a packaged device that's been burned-in.” Those statements could be from today, except that in 2002 there are perhaps some real answers to those challenges. Bull's-eye - In the first issue of Advanced Packaging in 1992, the news included one firm's projection for the growth in IC packaging from 1990 to 2000. Guess what – they were right. The Information Network of San Francisco, Calif., predicted that the 1990 volume of 29.9 billion packaged units would grow to 81.5 billion units in 2000. They were within a few percent, with the actual figure being 86.5 billion units, according to Electronic Trend Publications. The mix was a bit off, though, with the prediction being that dual in-line packages (DIPs) would decrease to 4 percent of the total by 2000. The actual figure was 12 percent. They also underestimated the resilience of SO packages, with the prediction of a 46 percent share in 2000 being short of the actual number of 61 percent. Apparently, it has been harder than expected to replace the previous generation of packaging with the many new technologies recently devised by packaging engineers.