Hillsboro, OR – Intel Corp. has unveiled several technology developments that it has integrated into its new 90nm process, which it says it has already used to build “record-breaking” silicon structures and memory chips.
Intel will put this process into volume manufacturing next year using 300 mm wafers.
This new 90nm process combines higher-performance, lower-power transistors, strained silicon, high-speed copper interconnects and a new low-k dielectric material. This is the first time, said Intel, that all of these technologies will be integrated into a single manufacturing process.
“We are moving ahead with the most advanced 90nm technology exclusively on 300mm wafers,” said Dr. Sunlin Chou, senior VP and GM of Intel’s technology and manufacturing group.
For more than a decade, Intel has been driving the pace of Moore’s Law by introducing a new process generation every two years. The 90nm process is the next generation after the 0.13-micron process, which Intel is using today to make the bulk of its microprocessors.
- Technology Breakthroughs
- Advanced transistors: Intel’s new 90nm process will feature transistors measuring only 50nm in length (gate length), which will be the smallest, highest performing CMOS transistors in production. By comparison, the most advanced transistors in production today, found in Intel Pentium 4 processors, measure 60nm. Small, fast transistors are the building blocks for very fast processors. These transistors feature gate oxides that are only five atomic layers thick (1.2nm). A thin gate oxide increases transistor speed.
- Strained silicon: Intel has integrated its own implementation of high-performance strained silicon into this process. By using strained silicon, current flows more smoothly, increasing the speed of the transistors. This will be the first process in the industry to implement strained silicon in production.
- Copper interconnects with new Low-k dielectric: The process also integrates a new carbon-doped oxide (CDO) dielectric material that increases signal speed inside the chip and reduces chip power consumption. This dielectric is implemented in a simple, two-layer stack design, which is easy to manufacture.
Process Breaks Records
In February, Intel used its 90nm process to make the world’s highest capacity SRAM chips at 52 megabits (capable of storing 52 million individual bits of information). These fully functional chips pack 330 million transistors in an area measuring only 109 square millimeters — about the size of a fingernail.
These chips also implement an SRAM cell size, measuring only one square micron — a milestone long coveted by silicon designers and manufacturers. By comparison, a red blood cell is about 100 times larger. Small SRAM cells allow for the integration of larger data caches in processors, which increase performance. These semiconductor devices were manufactured at Intel’s 300mm development fab (called D1C) in Hillsboro, Oregon, where the process was developed.
“Intel’s 90nm process is very healthy today and we are routinely producing these wafers and chips in our development fab,” said Mark Bohr, Intel Fellow and director of process architecture and integration. “By next year, we will be the first company to have a 90nm process in volume manufacturing.”
Other Process Details
Intel’s 90nm process also integrates seven layers of high-speed copper interconnects, which increase processor performance. A combination of 248nm and 193nm wavelength lithography equipment is used for this process. The company also expects to reuse about 75% of the process tools used on its current 300mm version of its 0.13-micron process, lowering implementation costs and ensuring a mature tool set for the manufacturing ramp. The 90nm process will be ramped into high volume in D1C and transferred to other 300mm manufacturing fabs starting next year.
Intel expects to have three 300mm wafer fabs using the 90nm process by 2003. One of the first commercial chips to be made on Intel’s process will be the processor codenamed Prescott, which is based on the Intel NetBurst micro-architecture and will be introduced in second half of 2003.