Solder bump inspection Evaluating new flip chip designs BY REZA ASGARI AND VASILE ROMEGA-THOMPSON Click here to enlarge image New flip chip designs can create inspection challenges. The Motorola Advanced Interconnect Systems Laboratory (Tempe, Ariz.), was given the responsibility of inspecting new flip chip designs and identifying any problems with the solder bumping process. Dimensions typically inspected include (in order of importance) bump height, bump coplanarity, bump size (diameter for circular bumps, length and width for rectangular bumps) and true position of the bump. Bumps also must be inspected for defects, which include missing bumps, bridged bumps, bump shape and nodules (Figure 1). A secondary inspection category is detecting defects on the surface of a wafer. Defects such as extra solder or foreign material on the wafer affect the reliability of the final package. It is important to determine bumped wafer characteristics accurately for statistical process control (SPC) use. It also is important to understand the defects caused by the process so that they can be controlled, increasing the final wafer/die yields and profitability. Fine-pitch ChallengesThere is a relationship between height and pitch. When the bump is collapsed there must be enough area around each to avoid shorts and other problems. Therefore, when bump patterns are created with smaller pitch, the bumps have to be shorter, and both height and diameter inspection need to be accurate. When dealing with dimensions like 110 µm effective pitch with bumps 75 µm in height and 90 µm in diameter, inspection can be a problem. Figure 1. Examples of solder bump defects.Click here to enlarge image At Motorola, the test lab was using manual optical systems to do this; focusing on the base and then on the top of each bump to calculate Z-height measurement – one bump at a time. When working with a wafer that had 1,000 die and 850 bumps per die, it was impossible to inspect all bumps manually and catch defective ones. Random sampling was being applied across the full wafer, typically consisting of measuring bumps at the wafer's top, center, bottom, left and right portions. However, in many processes it is imperative to inspect the full wafer. The plating process, for example, can be difficult because of the many input variables (solution flow, current distribution, bath temperature, pH, chemical reactions, element concentration, by-products, etc.). A sample inspection or random measurement will never show accurate cross-wafer variability. The entire wafer must be mapped to get an accurate picture of the functioning of the plating bath. Automated 2-D/3-D TechnologyThe lab had to find an inspection system that would accurately handle the measurements needed and, although speed was not an issue for lab work, the goal also was to find a system that could be used on the production line. Automated optical inspection (AOI) is fast, but not as accurate as desired. Near line metrology systems (when an inspection system is placed directly next to any particular station or stage in a full production line) are accurate but intrinsically too slow for continuous production inspection. There are many highly proficient defect wafer mapping systems, but most are designed for bare wafer mapping at the fab level. Figure 2. The RVSI WS Bump Inspection System was used by Motorola for the bumped wafer studies.Click here to enlarge image Motorola opted to beta test a dual inspection system that uses both 2- and 3-D inspection technology simultaneously (Figure 2). Using a proprietary 3-D laser and 2-D line scan camera, the entire wafer is scanned to provide data about bump height, size and defects. Generically referred to as a wafer scanning system, it was designed to inspect both bumped and non-bumped wafers, with the added capability of plotting micro surface defects at production level speeds. The system laser collects points in a 3-D space at a rate of more than a million data points per second, measuring height, coplanarity and any height-related bump defects. The camera focuses on the 2-D issues including diameter, bump location, missing or misaligned bumps, and defects within the bumps. Surface defects also are picked up by the 2-D lens. The system uses a graphical interface so when inspecting a wafer the user inputs the wafer/die size and then automatically determines the bump pattern, die pattern and associated issues. This was a significant reason the system was selected because both inspecting and teaching affect the total throughput. Substantial programming would have added greatly to the actual time running wafers. An automated wafer handling robotic system feeds the wafers into the machine and a vacuum chuck holds the wafer down during inspection. The system can handle wafer sizes from 100 to 300 mm at 100 percent inspection levels. The theory behind the system is that by using appropriate technology to inspect different features, it creates a blend of AOI and coordinate measuring machine (CMM) technologies. Using both in the same system keeps up inspection accuracy and throughput without sacrificing one for the other. Gage R&R StudyThe strength of any machine is its own variation when compared to process variation. There is better determination of process variation when the metrology variability is smaller. Figure 3. Stability of the bumped wafer inspection system over a nine-month period.Click here to enlarge image Motorola requires a period of incoming test for all equipment. Any system to be purchased or used in any way must be proven to meet or exceed specifications, i.e., the manufacturer's equipment variation level. The equipment variation must be small enough to enable accurate capture of any relevant process variation. This is done with an in-depth gage repeatability and reproducibility (R&R) test period in which the equipment is checked for accuracy. For example, a gage R&R at 10 percent would indicate that if trying to measure 100 to 120 µm bump height, of that 20 µm of process window, 10 percent of error comes from the system and the other 90 percent is true process variation. The gage R&R data for this system shows that it can control a process with a tolerance of 4 µm. Tight control is possible because the system is fully automated with no operator dependency. This provides a snapshot in time, but then the user takes it farther by measuring same-samples over time, in this instance measuring the same bump every week over a nine-month period. The standard deviation from that measurement over time is plugged in, giving a relative true variation of the system. The system tested at ±2 percent. Figure 3 depicts the stability of the bumped wafer inspection system over this nine-month period. ResultsIdentification of larger than normal bumps improved the yield of the wafer thinning process that followed wafer bumping in the process flow. It was found that even one larger bump could cause enough stress on the thinned wafer to break it.Non-uniform bump height was found to increase the probability of probe needles breaking during the known good die test, in which minute tip particles can become embedded in the wafer, causing fatal defects.When comparing samples of “plated vs. stencil” solder bumps (Figure 4), it was apparent that the stencil print did not have a center to edge variation, which the plated bumps did. Looking at coplanarity on both processes showed that the stencil coplanarity was an issue from the point where the squeegee started to the other edge of the wafer, rather than a radial variation.Because the coplanarity worsened as the squeegee blade moved across the wafer, it was apparent that there was a need to apply different pressure during the process, which was valuable information for the process engineer trying to reduce variability in production.A problem with a plating mask design arose that would not have been identified clearly without a full wafer scan. The design department had created a bump pattern in which a portion on the wafer purposely was left a larger metal pad area. The die around that metal pad area failed for low bump heights because the large metal plate, sitting on top of a plating bath, drew in most of the plating current, starving the surrounding area. The die neighboring that large metal pad failed because of “current crowding.” This would not have been readily apparent using sample testing.The design was sent back with instructions to eliminate metal plating or pads larger than a normal via in the design. This would improve plating uniformity.Both viewing and measuring the entire wafer presents a clear picture of what is happening in that plating bath. Flow patterns and wafer contacts are recognized in the plating bath by looking at the bump height center to edge of the wafer. Inspection Data In ProductionBumped wafer mapping can impact overall die cost by eliminating assembly and test for the defective die identified by the system prior to the dicing operation. The system also has been used for incoming inspection, by monitoring wafer contamination levels and tracking metal passivation defects. Bump height variation is the foremost problem faced in the production environment, with defective bumps second on the list. Bump height is critical in processing when putting chips into a package. Bump variations create a likelihood that the product will not work after packaging. Proper connections are not made; therefore, production cost increases dramatically because problems were not caught in time. Figure 4. Comparison of bump height uniformity for plating and stencil application processes.Click here to enlarge image The inspection data can be used for SPC tracking of wafer/packaging lots, and once there is a mature, well-understood process, a sampling plan can be developed. Depending on the scope of the SPC/process control program required at any company, this could be a minimum of checking several wafers from each lot to complete in-line inspection prior to final reflow. For the process engineer, the most important inspection data is bump height and diameter, which control the processing time variable. For assembly production, the most important thing is coplanarity. If one bump is 80 µm high and another is 130, there could be a problem when processing the die attach. Using a dual inspection process effectively addresses both areas. ConclusionThe camera/laser combination proved to be useful for catching missing bumps and other bump defects. It ensured full wafer mapping for surface defects, bump height, diameter and coplanarity, reducing potential problems in die attach. AP Reza Asgari may be contacted at RVSI Inc., 425 Rabro Drive East, Hauppauge, NY 11788; (631) 273-9700; E-mail: email@example.com. Vasile Romega-Thompson may be contacted at Motorola SISL, SPS, 2100 E. Elliot Rd., Tempe, AZ 85283; (480) 413-6417; E-mail: firstname.lastname@example.org.