Applications in interconnect and passive components
BY CHRISTIAN LINDER, DAVID FORK, CHRISTOPHER CHUA, KOENRAAD VAN SCHUYLENBERGH, CELINE VANDERSTRAETEN AND DARKO PLESA
A critical area of microtechnology is the mechanical stress of thin films. Generally, the goal is to keep the stress as low as possible for providing durable and reliable film stacks. On the other hand, it is possible to make use of highly stressed thin films. For instance, 3-D metal cantilevers with a built-in stress profile have been produced, resulting in structures bending out from the substrate surface as shown in Figure 1.1,2
Precise stress control in thin sputtered films is a key requirement for physical vapor deposition (PVD) tools such as the CLUSTERLINE single wafer sputtering system. Especially in the field of advanced packaging, such a system allows for fine-tuning of the stress by appropriate adjustment of various process parameters such as pressure, radio frequency (RF) bias and temperature.
In a joint effort, the Palo Alto Research Center (PARC) and Unaxis Semiconductors developed processes for the stress engineering of metal films. Technology details and potential applications are described in this article.
Material Property Control in PVD
An essential process step for metal nanospring fabrication is the sputter deposition of thin films with a large stress gradient throughout their thickness. As can be deduced from Figure 1, the films must change from compressive stress in their lower part to tensile stress in the upper part to protrude out of the substrate surface.
In interconnect technology, refractory metals and their compounds generally have high stress, e.g., Cr and NiV in the tensile region, while TiW or TaN exhibit large compressive stress. High-quality MoCr from the same material family has been chosen for the nanospring application.1,2 Hence, the process know-how for stress control over a large range can be directly used for the spring optimization.
Figures 2 and 3 illustrate typical results of the MoCr stress as a function of varying process parameters. Figure 2 shows how the stress is changed from large compressive values into the high tensile region by increasing the process pressure. In Figure 3 it can be seen how the application of RF bias to the wafer allows for reducing the stress from high tensile values to the compressive side. Applying additional wafer heating during the process pushes the stress again to the tensile region as further shown in Figures 2 and 3. This effect can balance out the partly nonlinear stress dependence on pressure and bias voltage. As a consequence, by adequate combination of the process parameters in the PVD sequence, maximum stress differences up to 3 GPa have been achieved, enabling the required spring behavior.
Regarding the specific resistivity of the MoCr layers, values between 20 and 30 µΩcm are measured at cold deposition, while heating during deposition allows decreasing below 15 µΩcm. These values are still higher than those of standard interconnect metal films such as Al or Cu, but also considerably lower than those of adhesion metals like Ti or barriers such as NiV or TiW. Conductivity can be improved significantly in view of potential interconnect applications by adding Au or Cu layers on top of the nanosprings.
Figure 1. The microstructure curls up to relax the intrinsic stress of the surface micromachined highly compliant MoCr nanosprings.
Figure 2. Stress characteristics of MoCr films as a function of process pressure and temperature.
Surface Micromachining for Cantilever Structures
Sacrificial layer technology commonly is used in the fabrication of freestanding microstructures at the wafer surface.3 The major processing steps include:
- Deposition and definition of the sacrificial or release layer on the substrate, which may be protected by a passivation layer
- Deposition and patterning of the microstructure film
- Removal of the sacrificial film by selective lateral etching, i.e., undercutting and selectively releasing the microstructure.
With surface micromachined MoCr springs, the microstructure finally curls up to relax the intrinsic stress, leaving a cantilever bending out of the substrate surface — forming the nanospring (Figure 1). Mechanical modeling and experimental tests on such stressed metal beams reveal that the force exerted by the spring tip can exceed many tens of milligrams. Because it is possible to machine very sharp points onto the springs, the contact pressure can measure in the thousands of kg/cm2. Figure 4 shows a protruding nanospring array after release. The cantilever lengths and widths are 200 and 60 µm respectively, and the bending height is 80 µm.
Figure 3. Stress characteristics of MoCr films as a function of RF bias applied to the wafer and for different temperatures.
Several additional technological issues needed to be resolved to meet the requirements of various nanospring device applications.1 For interconnect use, conductive release layers were introduced to place the nanosprings on wafers with integrated circuits (IC). Thus, the release layer can provide an electrical path between the metal contacts of the existing ICs on the wafers and the nanosprings. Also, it is possible to deposit the sacrificial and microstructure films in a continuous PVD process flow. Further, a dielectric is required to isolate and protect the pre-fabricated active devices. Organic dielectrics such as polyimide and BCB have been tested. The nanospring structures adhere well to these state-of-the-art dielectric and passivation layers used in advanced interconnect technology.
Ultimately, the implementation of the nanosprings with conducting release layers on polymeric dielectrics is a similar process to common interconnect techniques. This means only one extra mask (definition of the window for etching the release layer, as shown in Figure 1) is needed to add the self-assembled surface micromachined spring structures to the existing IC technology.
Application for Advanced Packaging
In recent years, packaging has increasingly moved from simple IC housing to an advanced technique that has to meet similar requirements as front-end technology: higher performance and better reliability at continuing miniaturization and reduced costs. In particular, wafer-level packaging (WLP) has developed to the point in which die and package are fabricated and tested on the wafer before dicing and assembly.4 Generally, WLP includes bumping technology for flip chip, with applications in the field of high I/O (microprocessors, high-end logic) and high-frequency as well as high-volume devices such as DRAMs.
Figure 4. Protruding MoCr nanospring array after release.
Stress engineered metal nanosprings may be promising candidates for WLP to satisfy the increasing needs in bonding pad density and performance. Major advantages include:
- Mechanical decoupling of die and substrate due to the highly compliant spring structures
- Scalability to ultra-fine pitches down to 6 µm
- Excellent electrical contact behavior at rather low contact force for Au coated contact points.
As previously described, this nanospring interconnect technology uses the same equipment as in common IC foundries and can be integrated to standard IC technology with only minor changes in the overall process flow. Flip chip packaging based on such nanospring interconnect structures has been realized with and without underfill.1
Contrary to conventional flip chip techniques, the underfill adhesive is applied in liquid form to the contact pads before assembling the package. Next, the chips with the released nanosprings are forced against the pads. During this compression, the springs also are aligned to the pads. Upon satisfactory alignment the adhesive is cured. This assembly sequence also is illustrated in Figure 5. A particular advantage of the Au coated nanospring contacts is that they allow the chip devices to be tested several times before assembly.
Figure 5. Assembly sequence for nanospring-based flip chip packaging.
Figure 6. Out-of-plane microinductors integrated with active circuitry.
Another interesting approach is the formation of flip chip interconnects without underfill allowing sliding against the contact pads. Such packages are highly resistant to the effects of thermal expansion. To avoid any contamination, perimeter bonded packages are used where the adhesive encloses the springs without making contact to them. Preliminary tests of such packages have been successful.
New Microinductor Device
Based on the above nanospring technology, PARC has developed an on-chip, out-of-plane (OOP) microinductor with superior quality (Q) factors and simplified manufacturing on a wide range of substrates. Figure 6 shows such a microinductor device integrated with active circuitry. This new coil holds many potential advantages for applications such as cell phones, TV tuners and wireless local networks. It also is suitable for other radio frequency integrated circuit (RFIC) and microwave applications.
3-D nanosprings have been fabricated by combining surface micromachining and controlled stress variation during sputtering of thin metal films. Potential applications of such microscale cantilevers include test probing for chip assembly and new types of passive components, as well as wafer-level flip chip packaging.
- D.K. Fork et al., “Stress Engineered Metal Interconnects,” 2001 International Conference on High-density Interconnect and Systems Packaging, Santa Clara, CA, April 2001, pp. 195-200.
- D.L. Smith et al., “A New Flip Chip Technology for High-density Packaging,” Proceedings, 46th ECTC, Orlando, FL, May 1996, pp. 1,069-1,073.
- C. Linder et al., “Review — Surface Micromachining,” Journal of Micromechanical Microengineering (IOP UK), Vol. 2 (1992), pp. 122-132.
- IMAPS 2002, Session: “Recent Developments in Wafer-level CSPs,” 35th Annual Symposium on Microelectronics, Denver, CO, Sept. 2002.
Christian Linder, Ph.D., Darko Plesa and Celine Vanderstraeten may be contacted at Unaxis Semiconductors, P.O. Box 1000, FL-9496 Balzers, Liechtenstein; +423 388 4364; Fax: +423 388 5415. David K. Fork, Ph.D., Christopher Chua and Koenraad Van Schuylenbergh may be contacted at Palo Alto Research Center (PARC), 3333 Coyote Hill Rd., Palo Alto, CA 94304; (650) 812-4121; Fax: (650) 812-4140.