BY RAO TUMMALA
Traditional packaging, as we know it, is beginning to change. I have always divided packaging into either integrated circuit (IC) or systems packaging. The new IC packaging technologies on the horizon are shaping up in two ways: 1) packaging at the wafer level, including wafer-level burn-in and test, and 2) system-in-package (SIP), or 3-D packaging of ICs.
Emerging IC Packaging Developments
The initial focus of wafer-level packaging has been on solders — both lead-based and lead-free. To guarantee reliability, the underfill technology, previously developed, is extending to the wafer-level process. Additionally, numerous approaches are being explored that do not require underfill. As the area-array pitch is reduced below 200 µm, and as the frequency of operation increases to 5 to 10 GHz, it is becoming clear that new concepts are necessary. Short-term approaches include compliant or spring-like connections. An example of this is the Sea of Leads approach1 being pursued at Georgia Tech and at Xerox Park. The SIP technology is being pursued at two levels: the packaged-IC level that is being developed by Fujitsu and Amkor and others, and the bare-chip stacking level that is being developed by ASET in Japan.
Systems Packaging Developments
Traditional board packaging with discrete components assembled by SMT processes is leading the way to more integrated systems packaging. This approach, initially pioneered by the Packaging Research Center at the Georgia Institute of Technology, is known as the system-on-Package (SOP) concept and is becoming a reality. The SOP concept proposes to improve system integration by embedding ASIC, DRAM, and passive and active components including filters, switches, and antennas as well as embedded optoelectronics such as VCSEL arrays, optical switches and waveguides. The first product introduction of this concept will contain embedded RF components. The first SOP product, named Simpact, is scheduled to be shipped by Matsushita in 2004. Even IBM, which invented the multichip module in the1980s, is moving to SOP, as evidenced by the November Issue of the IBM Journal of Research and Development.
A second technology that is being pursued involves embedding Optical Components in the board itself such as waveguides, gratings, couplers, dividers, switches and detectors, constituting an optical backplane, along with a mix of IC and RF components.
What Is Next?
Nanochips are well on their way. The front-end has been at nano-dimensions for a long time and back-end wiring is expected to enter production with sub-100 nm lines as soon as next year. Development of the first nanopackaging concept involves a three-way, international collaboration between Georgia Tech, NUS and IME of Singapore, and promises to bring nano-interconnects at the wafer level. A team of about 50 faculty, researchers and graduate students are exploring ways to develop nano-structured connections down to 20 to 100 µm pitch in the short term. In the long term, single crystal copper or gold wires, as well as nano-fibers are expected to reduce the pitch to 1 µm, providing unlimited connections and super bandwidth between chip and the rest of the system.
“Traditional board packaging with discrete components assembled by SMT processes is leading the way to more integrated systems packaging.”
In the not so distant future, we will see untethered medical diagnostics, monitoring and treatments based on nano-SOP packaging — wireless computers that are hardly larger than a wristwatch and wireless, multifunction medical implants that are no larger than a dime to be used for daily monitoring and treating. The future relentlessly challenges us.
1Proceedings of the IEEE 2001 International Interconnect Technology Conference, Burlingame, CA, June 4-6, 2001, pp.151-3.
Professor Rao R. Tummala, president of IEEE-CPMT Society, is a chair professor in electrical and computer engineering and materials science and engineering and Founding Director of the Microsystems Packaging Research Center (PRC) funded by the National Science Foundation at the Georgia Institute of Technology, Atlanta. He may be contacted via e-mail at firstname.lastname@example.org.