Leadframe Chip Scale Packaging

Many new packages, many expectations


The proliferation of new packaging families and variations today is more rapid than ever before. Demands on cost, performance, density and matching to specific chip technologies or applications present the IDM designer with an ever-widening pallet of choices. While this is good from a cost/performance perspective and allows the designer to select an optimum solution, it also introduces some level of confusion. Many of the new packages appear similar upon cursory examination; yet often present widely different expectations depending on the construction technique and the required application.

Advantages of QFN Packages

The first CSP was the saw singulated ball grid array package (fpBGA). This package offers good densities and acceptable performance for most applications, but the requirement of expensive BT substrates for the assembly limits the downward cost trends expected in today's market. The first of the leadframe CSPs, the quad flat no-lead (QFN) package, addresses many of those concerns. The package is based on a leadframe assembly, and hence the cost per package area can be substantially less than the bismaleimide triazine (BT)-based fpBGA, and the electrical performance is substantially improved. This is the result of direct signal paths from the top of the die to the backside of the solder connect pad; unlike the convoluted path through various vias and multiple metal layers taken with a fpBGA package. Similarly, the thermal path on a QFN is direct from the backside of the die, through the die attach pad (DAP) and directly down to the DAP land on the motherboard. The two charts in Figure 1 compare electrical inductances and thermal impedances in many similar density packages. The performance advantages of the QFN vs. the fpBGA are clear.

Cost of Ownership

Cost of ownership is a key consideration when choosing an integrated circuit (IC) package. Simply looking at the cost of Package A vs. Package B does not capture near the total picture required to make the best selection. Cost of ownership includes the cost of the package, test, relative reliability risk (quality) and motherboard routing efficiency. The cost of the package is relatively straightforward, and an easy gauge of this is the cost charged for QFN packaging by the many subcontract assembly test houses that currently offer QFN packaging. The cost of test can be more difficult to gauge. Current trends see a large advantage in strip test for low- to medium-I/O count products. This is a result of the higher efficiencies of strip test as well as the observed test accuracy improvement in strip test (handler related miss tests are greatly reduced). FpBGA packages usually have plating busses in the saw street, and hence are not compatible with a strip test. QFN packages can be strip tested, but it depends on the format of the specific package as to how to accomplish this. Punch singulated QFNs require a “pre-punch” to isolate the leads from the tie bars before strip testing, and saw singulated QFNs require an “iso-cut” partial saw prior to strip test.

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Figure 1. Electrical inductances and thermal impedances in similar density packages
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Cost of Quality

Cost of quality is another important consideration when choosing a package. FpBGAs are mature products well down the learning curve. QFNs today are also becoming mature, but the QFN package has inherent features that make ensuring quality somewhat more difficult. For one, the stress field at the point where the die, the DAP and the mold compound come together is very high during temperature excursions such as moisture sensitive level (MSL) or board mounting. The copper DAP is directly exposed to the temperature excursion and expands at a high coefficient of thermal expansion (CTE) rate. The die expands much less due to the low CTE of silicon, resulting in a high stress field. The result is the QFN package requires special care to ensure that the DAP does not delaminate. One assembly and test (AT) supplier* has developed control methodologies to allow for general leadframe-based products to achieve MSL 1, and these procedures ensure that even with the high-stress fields of leadframe chip scale packages (LFCSPs) no DAP delamination is observed. Another consideration on QFN quality is the technique for singulation. Both punch and saw are used in the industry. While the sawing technique is more expensive due to lower assembly throughput, sawing produces a high-quality and reliable package consistently. Punching can also produce a good quality package, but cutting through the silica-filled plastic is wearing to the punch toolings, and as the punch wears, the chance of delaminating the I/O land pad from the package body increases.

Routing Efficiency Cost

To find the cost of routing efficiency, the motherboard requirements for various package choices must be considered. Taking for example an 80 to 100 lead device, we can use a 14 x 14 mm TQFP (that requires 16 x 16 mm board area), or we can use a fpBGA that can handle 100 leads in a 9 x 9 mm package or even less. QFN or chemically milled packages (CMP) can meet this density in an 11 x 11 mm or 7 x 7 mm format respectively. It is important to consider the motherboard design rule densities. In fine-pitch full-array BGA packaging, the routing of internal balls pads requires multilayer and blind via substrate technologies that increase cost significantly. In addition to the area of the motherboard required to support the number of packages, the density of the motherboard is a consideration. In that case, the peripherally routed QFN or CMP packages allow a simpler routing task compared to fpBGA packages where center balls can become “trapped” by outer balls. Another consideration is system performance. Higher package densities allow for tighter motherboard densities and the closer proximity of adjacent packages reduces the signal path from one IC to another on a system level. This improves electrical performance and allows for a smaller finished product.

Chemically Milled Packages

The next stop on the evolutionary path for leadframe CSPs, the chemically milled package (CMP) technologies of a bumped chip carrier and an array plastic package. Both technologies are leadframe-based, and are not limited to a single row of peripherally located I/O pads. They can, in fact, have several rows and in multi-chip multi-layer (MCM) applications permit I/O pads in the center of the package. These packages offer basically the same electrical and thermal performance as QFN packages as a result of having a similar cross sectional construction. The advantages of CMPs lie in density, flexibility and cost per I/O. The ability to have multi-row layouts greatly extends the I/O range of a leadframe CSP from 64 I/Os for a QFN into the range of several hundred I/Os for a CMP. Another advantage is the natural affinity for strip test. No preparation is required. During assembly, the molded strip is available in a completely strip test-compatible format for both the bumped chip and array technologies.

CMP packages also offer advantages in the low I/O range. Because the DAP does not require a tie bar, the corner spots on a QFN layout can have functional I/O pads. For every package, there are four additional I/Os available. CMPs in the range of 1.5 x 1.5 mm offer designers a range of high-density products, especially for the array package, which is available in a maximum thickness of 0.4 mm.

As before, a cost of ownership exercise should be taken with regard to CMPs. Generally, both bumped chip and array can occupy the same outline drawings as each other; however, their construction actually proceeds down considerably different paths. While both packages achieve their final format via a chemical milling or etching process, the I/O interconnect process is different. In bumped chip carriers, pre-etching a pocket in a leadframe carrier and then plating the I/O metal structure in the pocket forms the I/O pad. This plated pocket then accepts the gold wire stitch bond by pre-wirebonding and flame off of a gold ball in the pocket. The advantage is that the resulting package has a built-in 3-D standoff relative to the motherboard. The disadvantages are the complexity of assembly with two wire bonds required per I/O, density limitations below 0.5 mm pitch and impact test concerns due to the lack of a mechanical interlock of the plated I/O metal structure to the molded package body.

Figure 2. Bumped chip vs. array technologies
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In comparison, growing the plated metal stack on a flat leadframe carrier makes an array package. The plated structure is designed to overhang the organic plating mask in such a way that the I/O pad structure displays a “rivet” formation for mechanical interlock. This structure does not require two wire bonds per I/O, but allows for higher densities.

As for QFN, part of the opportunity cost assessment is in risk factors. Bumped chip carriers offer a wider customer base as well as a bumped standoff for reduced stress on the solder joint. Arrays offer the mechanical interlock of the I/O pad as well as an adhesion promotion process to counter the high stresses at the DAP-to-die interface caused by mismatched CTEs.

QFN packages are seeing several new developments. One is the paper-thin package (PTP), which is 0.25 mm thick, interconnected in either a die up or die down format, and is compatible with pretested stacked package configurations. This package may find a strong following in the boutique memory market. Other QFN flavors on the horizon include solder bumped I/O pads using a screen-printed solder paste bump before singulation. This format offers many advantages regarding the reworkability and second level reliability of the finished assembly.



NELSON FAN, vice president of engineering, and NEIL MCLELLAN, chief technology officer, may be contacted at ASAT Holdings Ltd., e-mail: nelson_fan@asathk.com and neil_mclellan@asathk.com.


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