BY BOB FENTON
The goal of saving time and money by conducting final test in strip or matrix format can be achieved by applying prober-based sort floor technologies and methods to final test handling. While today's sort floors can process multiple types of devices in the same physical format, a wafer, final test has a proliferation of multiple handler types for each package family. By adapting sort floor technology, probers in particular, for use during final test, manufacturers can achieve uniformity of material handling in final test. This results in greatly reduced costs and far less material-handling overhead. Combine this change with another sort floor benefit, the ability to use software maps to track the individual device yields, and you have a convincing case that wafer sort floor technology will drive the eventually successful conversion to strip testing.
Traditional Test Handlers
The first test handlers were gravity-fed machines designed to process dual in-line packages (DIP). As packages evolved, so did gravity handlers. The base concept was to have the packages slide down an inclined rail to a retractable stop where they were touched by electrical clamps for testing. Below the test site there was a shuttle, revolving belt or other mechanism to transfer the tested parts to the appropriate bins. These machines were testing single devices to match the typical capability of the testers of the day. For memory applications, testing soon evolved to four test sites. Packaging was still mainly DIP.
Within a few years, board technology started to migrate to surface mount, bringing up new packages. For the J-lead and gull wing style of in-line packaging, gravity handler technology evolved to fill the handling needs. At the same time, quad and array packaging started to gain popularity. Gravity handlers attempted to deal with this new technology by using carriers or nests to protect the device leads during handling, or by using “decelerators” to reduce device speed when the leads contacted the stops. The decelerator approach was reasonably successful, but really only for robust quad packages like the plastic leaded chip carrier (PLCC) and ceramic leadless chip carrier (CLCC). This technique reduced throughput, but made for safe handling. For packages where carriers were used, the carrier was often molded into the package during assembly and then removed after testing — adding extra material, or at least an extra process step. Much like the conversion to strip testing today, by the middle of the 1980s it was becoming apparent to most test and manufacturing organizations that a new paradigm for handling was required, although many industry diehards resisted the change to pick-and-place technology.
The first commercially successful pick-and-place handlers were produced in the mid-1980s. The success of these early systems brought about a number of robotic gantry pick-and-place handlers from several manufacturers. As pick-and-place and gravity handlers evolved, they diverged even further.
Testing also continued to evolve, with increasing parallelism becoming the norm. Today, most gravity handlers have variants that support four test sites for short test time products, and pick-and-place handlers have further specialized to handle either short test times with up to eight units tested in parallel, and long test times using 16 to 64 test sites. Within the pick-and-place category, there are two distinct types. As testing continues to evolve, even more diversification and specialization will likely occur.
Gravity and pick-and-place handlers for short test time applications have high-speed sorting sections, up to 28,000 units per hour for gravity handlers. Unfortunately, most test applications limit the throughput because of low sorter utilization, which is caused by long test times and limited number of test sites.
As packaging continues to evolve, chip scale packaging has become more prevalent. Average die sizes have become smaller in all but some memory applications (where density has increased with about the same die size). The die size decrease and new packaging has brought about dramatically smaller packages. The chip-to-board interconnect capabilities have also become smaller, allowing chip designers to use even smaller footprints. With the increasing popularity of portable electronics, packages will continue to shrink.
The current result of test handler evolution is that handlers are now application-specific, not only for package type but also probably for test application. Further, they need to take devices out of transport media such as tubes or trays one at a time and assemble them in an array of 4-64 devices and present them to a test system. Packages are already in arrays during assembly, eliminating this time-consuming step to allow testing in parallel. This does not mean that traditional handlers are going away, but instead that semiconductor manufacturers and test houses can save money and time by using high-speed sorting handlers in applications where they are not held back waiting for tester output.
Traditional Wafer Probe
Wafer probers have enjoyed a tremendous advantage, but also some difficulty not encountered by handler manufacturers. Compared to packages, all wafers are effectively the same, which would appear to make the handling task easier. The actual handling task, though, is probably more difficult since wafers are extremely fragile and damaging even one wafer is unacceptable due to the large number of valuable die lost. Additionally, the accuracy required to align probe pins with bond pads is much greater than that required to align a package lead to a contactor. Today, reliable and consistent touchdowns are required on targets as small as 30 µm, as in probing gold bumped liquid crystal display (LCD) driver applications.
In yesterday's sort floor, failed die were identified by an ink dot, which indicated that they should not be packaged. Most device functional testing was performed after final packaging using this method. Further, there was a belief that final electrical testing could prevent packaging defects from reaching the market.
Tester, load board and, most importantly, contactor and probe card technology have evolved to the point that for many applications high parallel test is indeed possible in very dense test arrays such as wafer or strip format. New testers are available today that challenge long- held standards of costs per pin, making higher parallel testing very attractive.
In the 1980s, certain memory chips began to be screened to multiple bins at wafer sort. This change brought widespread use of electronic wafer maps to track the test results of die on a wafer. Today, most sort floors rely entirely on electronic maps transferred from sort to dicing and die attach. With the exception of those visionary companies adopting strip methodology, final test by and large still relies on color coded tubes and trays, operator diligence and test floor housekeeping to track good devices from bad after testing. If maps work at wafer sort, shouldn't they work in final test?
The use of an electronic wafer map forms the basis for the 1990s paradigm of a data centric sort floor, where yield, throughput and costs are dramatically improved through automation. Today it's possible, and perhaps even commonplace, to manage a sort floor remotely using map-based comparisons either in real time or statistically. Comparisons are made based on die location, process step and yield, giving an operator or technician clues to process issues before a large amount of material is tested improperly. User-defined rules are often applied, for example correcting high probe pin resistance due to foreign material buildup by automatically cleaning the probe card based on high occurrence or percentage of a particular yield or bin code. Another example is intelligent re-probe, where wafer tests are repeated automatically based on predefined rules before the wafer in process is unloaded from the test chuck. Also, maps and data can typically be compared over an entire floor of many probers, so process issues become visible sooner or precursors can be detected and corrected prior to a system or lot event (Figure 1).
Figure 1. SEMI G84-compatible strip map
There are several corollaries of these examples to final test. Once the conversion has been made to a map-driven process, the link between wafer, assembly and tray maps can be made enabling individual die traceability (IDT), for example.
Probers are routinely controlled via a network interface where they automatically load the appropriate product files and test routines based on analysis of the wafer they have loaded.
Traditional Package Assembly
Many original versions of plastic package assembly lead frames contained 15 or fewer devices. This limitation was due to the lead frame format (35-mm width), relatively large package size and the fact that nothing was really driving the need for improvements. These limitations were the norm up until a few years ago when some leading companies started building larger and higher density lead frames. With new packages as small as 1 x 2 mm and strip geometry as large as 70 x 250 mm and even larger, there can be hundreds of devices in a strip. In the past, no consideration was given to the electrical properties of the strips — that was for package testing after singulation.
Today, strips are configured specifically for testability at many assembly facilities. Testability requirements include strip density, individual device isolation, thermal properties and other considerations.
Based on the existing states of these three areas — prober technology, packaging technology and handling — there is a convergence point centering on wafer prober technology. Considered globally, a contiguous batch of 40 to 2,000 “test targets” in a rectangular or round shape has the same handling problems. For example, a 6″ wafer with a 6.5-mm die size contains about 280 to 350 testable die, while a 10 x 30 high-density 0.150″ small outline integrated circuit (SOIC) lead frame has 300 parts. In terms of surface area, they both measure approximately 175 cm2. Of course, it is a lot easier to contact the SOIC leads than the bond pads on the wafer.
Other high-density packages are micro lead frame (MLF), quad flat no-lead (QFN), micro ball grid array (µBGA) and thin small leadless package (TSLP) — all capable of having 96 to 200-plus devices in a strip, depending on specific package size. At the fine pitch side, these packages have wafer level test structure targets down to 150 µm and below. According to the 2001 ITRS Roadmap for Assembly, ball grid array (BGA) and chip scale package (CSP) bump sizes are currently as small as 160 µm and will approach 100 µm in the next 10 years.
In effect, strips are rectangular wafers. The uniformity that this approach gives to handling is significant; there are currently more than 12 major gravity and pick-and-place handler manufacturers, while there were only a few prober manufacturers for many years.
A difficult strip handling challenge is the following etched frame TSLP, where the substrate bus lines shorting the parts have been etched away. The individual device size is quite small, approximately 1 x 2 mm. Additionally, the isolation process divided the existing strip into substrips ~50 mm square, in a 56 x 36 array of 2,016 devices.
Similar to the previous example of a high-density SOIC lead frame, that is a strip even more like a wafer. Its small bumps are 150 by 250 µm, requiring prober precision. Initial correlation results indicate a very high degree of correlation, with about four devices out of 30,000 being outliers. This is probably due to the contacting precision and overall test system effectiveness (Figure 2).
Figure 2. Contact mark example
Theoretical strip handler throughput (single site testing) can be calculated in the following manner:
Strip index time = “S” seconds
Strip Index time is the material handling time plus the alignment time.
Test cell time = “T” seconds
Test cell time comprises the test time and communications overhead, plus the interstrip index time, provided there are more devices present in the strip than are tested in one insertion.
Throughput in units per hour is 3,600/(T+ S/number of devices in strip)
Figure 3. Graph showing TSLP throughput
Throughput based on test times (Figure 3):
A comparison of these results with a singulated test handler is probably not possible because of the package geometry. A singulated package handler would be severely challenged trying to hit these very small test structures using mechanical alignment. Other packages such as a 0.150″ SOIC could be tested in strip format or in a singulated handler, so there is value in a comparison of the throughput of these two methods. If it were possible, the fastest index time would be about half a second, giving the following (theoretical) results (Figure 4):
Figure 4. Graph showing theoretical gravity throughput
Of course, the throughput converges with increasing test times; meaning that the longer the test time, the less handling overhead matters. For longer test times, however, strip test — like wafer probe — has the benefit of being able to accommodate parallel testing without changes to the handling system.
The main enabler at work for strip testing is technology migration. In the wafer prober arena, we've seen that wafer fabrication technology is now required to probe 300-mm wafers in production due to decreasing geometries and throughput/cost pressure, and also are observing that probers are required to probe package strips at final test for the very same reasons. The main difference is that wafers are already matrices of densely packed die. Strip test represents a way to dramatically change final test for the better. Handling of individual devices should be done only to sort them, maximizing test cell throughput, tester utilization and efficiency.
With many industry experts predicting that test, assembly and packaging costs will become 50 percent or more of the cost of a finished device, strip testing is an attractive solution. Prober technology, applied correctly, will make strip test a reality.
BOB FENTON, director, may be contacted at Electroglas Inc., 6024 Silver Creek Valley Rd., San Jose, Calif. 95138; (408) 528-3887; e-mail: email@example.com.