NEW TECHNIQUES FOR ELECTRONIC DEVICE SAMPLE PREPARATION
BY TIM HAZELDINE AND KIM DUONG
The seemingly unquenchable thirst of semiconductor manufacturers for faster and more powerful microchips places great demands on required semiconductor manufacturing processes. The increasing use of 12-inch-diameter silicon wafers that offer improved production yields, coupled with the increase in the number and packing density of transistors on each die, further increases the demand to provide scalable process solutions. To achieve necessary processing performance speeds, modern IC circuitry is produced through multiple layers of metallization. This raises the bar for production, as well as for failure analysts responsible for finding submicron defects hidden within a maze of circuitry.
In this article, the main sample preparation disciplines required for electronic failure analysis are discussed, as well as the ways in which mechanical preparation equipment has evolved to fit the challenges offered by the complex set of materials that form the modern IC package.
Production of quality cross sections on package-level, wafer-level and board-level devices generally begin with a saw cut. Precision sawing dictates the level of surface damage and surface features retained. The resulting surface may be an end in itself — a good sawed surface offers information for generating a selected area preparation process — or the starting point for polishing. Saws range from manually fed trim saws to advanced semiautomatic dicing units.
Successful cross-sectioning techniques maintain important information within the die or package, while being sufficiently controllable and reproducible. Non-encapsulated cross-sectioning, particularly on die-level devices, is faster and easier to perform than encapsulated methods — yielding suitable results for scanning electron microscopy (SEM) and transmission electron microscopy (TEM) analysis.
Figure 1. Precisely milled sections of multilayer PCBs allow for electrical connection and, therefore, analysis of circuitry that would ordinarily be unreachable.
Cross-sectioning product offerings include manual and semiautomatic approaches, with advanced wedge-angle and low-inertial sample loading controls. These systems suit both encapsulated and non-encapsulated sample types. Techniques are available for the key process steps of precision sawing, grinding and polishing that allow low-relief preparation of materials with widely disparate hardness and other mechanical properties.
As electronic device sizes shrink, the deprocessing operation becomes more exacting. Over the past few years, metallization has moved into the submicron realm, which means that the 1-µm resolution limit available with mechanical indicators is obsolete. Methods have been developed to ensure that submicron parallelism of a device under preparation can be maintained — even down to 0.1 µm for die sizes less than 9 mm.
A chemical mechanical polishing (CMP) approach addresses another key weakness of previous metallurgical-polisher-based systems in the marketplace, namely sample edge rounding. The use of a true, flat lapping bench-top CMP system with a polyurethane-based pad material allows for improved overall flatness and removes edge rounding.
Figure 2. Thinning a silicon substrate to less than 80 µm allows the backside microscope to image circuitry under near-infrared illumination.
The majority of mechanical deprocessing, however, relies on a skilled analyst working with manual polishing tools.
Topside decapsulation (analysis performed on the circuitry-populated side of the wafer material) by chemical means is a well-established application carried out with manual protocols or, more frequently, with automated acid etch systems. These methods produce fast and effective results on standard plastic packaged parts. Several factors, however, make acids incapable of processing all package types. When a package contains materials that seem impossible to remove with acids, or when the total packaging cross-sectional thickness is large (exacerbating the nondirectionality of acid attack and potentially leading to harmful corrosion of bond pads and wires), initial mechanical decapsulation offers key advantages.
Figure 3. A standard selected-area preparation system uses a small rotating tool oscillating within pre-defined amplitudes to produce a cavity within a chip, and then polishes the surface.
After discovering that many decapsulation applications benefit from initial mechanical operations, dedicated processes were developed for multi-chip modules, stacked die chip scale packages, multilayer PCBs and power devices based on the selected area preparation product platforms (Figure 1). These systems provide control of all required parameters to increase electrical survivability and yield in many decapsulation applications.
The increasing number of metallization layers used in modern ICs, which physically block the view of microscopes from seeing faults and point defects, rendered front-side techniques inadequate for complete failure analysis. Backside imaging is possible because pure silicon is transparent at near-infrared wavelengths. Dopants added to the silicon substrate to alter electronic characteristics of the wafer reduce this transparency. To image a modern die effectively with a back-side microscope generally requires planar thinning of the wafer from a nominal 500-µm starting thickness down to 80 µm or less, followed by polishing (Figure 2).
Backside imaging is an evolving field that encompasses emission microscopes (with silicon CCD or compound semiconductor detectors) and laser scan methods to locate smaller defects by a characteristic generation of light, voltage/current change or thermal change. Focused ion beam equipment is also being used to make topside and backside circuit modifications, based on a map made by overlaying the backside image over the part's circuit diagram.
Backside Selected-area Preparation
Backside analysis on packaged or encapsulated dice requires decapsulation and heat sink milling prior to substrate thinning. Processes have been developed that enable effective, low-damage backside preparation techniques for dice of all sizes and with all encapsulation techniques.
Figure 4. a) Typical backside image without an anti-reflective coating. b) Same area of sample after anti-reflective coating.
After producing a mirror polish on the decapsulated and substrate-thinned package/die, the resulting sample is backside-imaged with near-infrared illumination (Figure 3). However, glare from the polished surface reflected into standard objective lenses prevents good image contrast. The addition of an anti-reflective coating provides both improved contrast and, moreover, a significant increase in photon efficiency evident from emission sites. Until recently, anti-reflective coatings required expensive sputtering equipment and subsequent baking at high temperatures. Technologies are available that put quality anti-reflective coatings within easy reach of every sample preparation laboratory (Figure 4).*
The sample preparation of electronic materials in packaged and wafer forms is increasingly challenging because of the continued evolution of semiconductor manufacture. Metallurgical-grade equipment no longer provides the flatness and parallelism results required to delineate layers of modern circuitry for topside applications. The required finishes are achieved by using flat-lapping equipment and optical measurement tools.
In backside applications and decapsulation of ball grid arrays, flip chip and CSP packages, the use of selected area preparation systems enables access to the circuitry for both topside and “through the wafer” analysis.
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TIM HAZELDINE and KIM DUONG, applications specialists, may be contacted at ULTRA TEC Manufacturing Inc., 1025 E. Chestnut Ave., Santa Ana, CA 92701; (714) 542-0608; e-mail: email@example.com and firstname.lastname@example.org.