Wafer-level Hermetic Cavity Packaging

Potential cost, handling and performance advantages


Wafer-level hermetic cavity packaging offers potential cost, handling and performance advantages in packaging a wide variety of MEMS, optical and sensor devices. As the cavities grow smaller, however, the technical challenges grow larger. This inverse relationship has led to many proposed technical approaches. Which will become favored in the marketplace is as yet undetermined.

Conventional wafer-level chip scale packages (WLCSPs) combine the chip scale package advantages of small size and ease of handling with an efficient production approach based on batch packaging at wafer level. The essence of WLCSP is that the packages are created directly on the wafer, before the wafers are sawn into individual units. In creating the package, additional layers of material may be deposited over the active surface of the die. The resulting savings in size, weight and money have led to wide acceptance of WLCSP, primarily for small- to medium-size die with low input-output (I/O) requirements.

WLCSP offers even more advantages for packaging devices that have active surface features. In addition to the size, cost, and performance advantages of conventional WLCSP, wafer-level packaging with a protective cavity adds mechanical protection, beginning at the wafer level, for devices with fragile surface features, such as MEMS, optoelectronics and sensors. Some of these devices require a controlled atmosphere in the cavity, while others function best in a vacuum. Wafer-level packaging of vacuum cavities brings the cost advantage of simultaneously sealing an entire wafer of cavities in vacuum. This eliminates the manufacturing inefficiencies and the costs of individual “pump down and pinch off” for archaic metal or ceramic vacuum packages.

These potential cavity package advantages have sparked many development efforts for wafer-level hermetic cavity packaging. The earliest cavity WLCSP to be produced in large quantities were for protecting MEMS devices with moving surface elements. Millions of automotive airbag systems are today controlled by MEMS accelerometers residing in hermetic cavity wafer-level packages. More recently, cavity non-hermetic WLCSP support high-volume consumer applications, such as digital cameras.1 Controlled-atmosphere hermetic cavity WLCSPs are currently being offered for MEMS RF switches.2 Further developments aim at size, weight and cost reductions for limited-lifetime products, or at economically meeting the more stringent requirements of high-performance, long-lifetime MEMS, optical devices and sensors.

Since cavity WLCSP by their nature are generally precluded from adding layers over the active devices on the wafer surface, cavity packages are created either by bonding a second wafer with pre-formed cavities over the device wafer (wafer stacking) or by dicing the second wafer and bonding the individual cavity chips onto the device wafer (chip-on-wafer). Both approaches are discussed in this article, along with a variety of non-hermetic, near-hermetic and hermetic sealing methods.

Challenges of Hermetic Cavity Micropackaging

Creating, maintaining and measuring a high vacuum or a stringently controlled atmosphere in nL-scale cavities poses challenges unique to wafer-level cavity packaging. For example, the hermeticity test of MIL-883E, Method 1014.9 is invalid for cavity volumes under 1,000 nL.3 The low-nL cavity volumes typical of advanced devices will require new methods for determining hermeticity. In addition, leak testing is only one of the concerns in controlling cavity atmosphere over long lifetimes. The materials and seals used must be leak-free, impermeable and not sources of significant out-gassing, both during assembly and over the expected operating lifetime. The high surface-to-volume ratio of cavities at these dimensions exacerbates the difficulty of establishing and maintaining the desired atmosphere. Surfaces are reservoirs of adsorbed gases such as oxygen, carbon dioxide and reactive gases. Plated metal components are major sources of dissolved hydrogen, a potential device-killer. Extended vacuum bake-outs, adsorbents in the vacuum chamber, and getters as part of the package are among the remedies used.

A recent paper described high-vacuum packaging of MEMS inertial sensors in leadless ceramic chip carriers with brazed metal lids.4 The required operating lifetime of these sensors is 20 years, which for the chip carrier package requires a gas leakage rate of 10 to 13 standard cm3/s. A single monolayer of carbon dioxide on the proof mass of a 1-µg sensitivity accelerometer can cause an unacceptable error. The sensor was gold-bump mounted, to avoid trapping gas. An extended degassing bake-out in high vacuum was required to reduce dissolved gasses in the materials. A non-evaporated getter was included in the cavity, to absorb gas molecules that diffuse into the cavity or are given off by internal components. The stringent methods required to achieve and maintain a cavity pressure below 10 mTorr in these larger packages are indicative of the challenges facing high-vacuum cavity micropackaging.

Varieties of Cavity Micropackaging

A direct approach to fabricating a wafer-level cavity package is to adhesive-bond a cover wafer that contains etched cavities on its surface over a wafer containing active devices. One example appears in WLCSP cavity packaging of image sensors and optical detectors. CMOS and CCD linear and array sensors for commercial applications are packaged in a glass-silicon-glass sandwich, laminated and sealed with epoxy. The top glass wafer provides an optical window. The bottom glass wafer brings out solder bump contacts in a ball-grid array on the bottom side of the die. Because of the permeability and possible outgassing of the epoxy seals, the package is classified as non-hermetic. However, these packages are in volume production for CCD digital cameras, CMOS-based sensors and other commercial applications. They appear to be adequately meeting the needs of the consumer market.

A near-hermetic cavity with cost, weight and performance advantages uses a liquid crystal polymer (LCP) substrate, cap and seal.5 LCP is a thermoplastic polymer with barrier properties an order of magnitude greater than epoxy plastic materials.6 The permeability of LCP to water vapor and to oxygen is close to that of glass. LCP combines the light weight and low cost of a polymer with suitable dielectric properties and protective capabilities. The cavity LCP package draws upon well-established LCP printed circuit board (PCB) technology for a multilayer base, integrating high-speed cavity feed-throughs into the substrate itself. The components and circuitry are protected by an LCP cap, which forms the cavity.

LCP packaging allows a unique method of sealing the lid assembly. The LCP may be laser-welded at the bond line, using an infrared (IR) laser to create the seal. LCPs are transparent to IR, so the beam passes through the cap with minimal absorption. An IR-absorbent material is added to the LCP at the bond line, localizing heating to the immediate seal area. The welded seal is formed from the LCP material. Figure 1 shows the elements of a welded-seal LCP package: the substrate, the cavity, the lid and the completed assembly.

Figure 1. Elements of an LCP package designed for laser-weld sealing: the substrate, the cavity, the lid, and the completed assembly. Photo courtesy of Foster Miller, Inc.
Click here to enlarge image

Sealed LCP cavity test vehicles have passed helium leak testing, per MIL-STD-883E. However, as noted above, this standard is inappropriate for polymer packages, because it measures only fine and gross leaks, with no consideration of permeability, outgassing or absorption. Pending resolution of this hermetic terminology problem, LCP packages are considered “near-hermetic” or “quasi-hermetic,” poorly defined terms for packages suited to applications not requiring extended lifetimes.

Another near-hermetic microcavity package seals the cavity caps onto the wafer with the photopatternable polymer BenzoCycloButene (BCB).7 BCB shows minimal outgassing, low moisture uptake and excellent electrical properties. Its flow characteristics during curing provide a good seal for signal feed-throughs. In one process, the BCB is spin-coated onto the capping wafer and photopatterned to provide seal rings. The capping wafer is diced, and the capping die with seal rings are aligned, placed, and tack-bonded over the MEMS devices. Reflow of the BCB at 250°C in a controlled atmosphere or vacuum completes the assembly.

Microbolometers and RF MEMS switches have been packaged in BCB-sealed cavities. Figure 2 shows a portion of a microbolometer wafer, with BCB-sealed caps over some devices. Liquid biosensor cavity wafers have been BCB-sealed using glass caps patterned with fluidic channels over the sensors. BCB-sealed cavities established the failure of MIL-883E hermeticity testing at small cavity volumes, and allowed investigation of alternative hermeticity measures.

Figure 2. A portion of a microbolometer wafer, with BCB-sealed caps over some of the devices. Photo courtesy of IMEC and XenICs.
Click here to enlarge image

The highest production-volume hermetic cavity wafer level packages are those for MEMS accelerometers in automotive airbag systems.8 This wafer-level package is created by making a glass frit seal between the MEMS wafer and a cap wafer. The approach is similar to the long-established use of glass frit as a seal in conventional hermetic ceramic packages. The difference is that now the glass frit forms as well as seals the cavity walls between a cap wafer and a device wafer.

The cap wafer is stenciled with a mixture of glass and binder, patterned to be the walls of each device cavity. Firing the stenciled wafer sinters the stenciled glass onto the cap wafer, forming the cavity walls. In assembly, the glass cap wafer is aligned and thermo-compression bonded to the device wafer, with the glass frit making the hermetic seal. The glass frit seal accommodates raised metal traces passing under the seal, and may be sealed in vacuum or in a controlled atmosphere. A similar glass-frit cavity package with a controlled atmosphere is available for RF MEMS switches. Limitations on extending the frit-seal approach to more challenging applications include the large size and footprint required for a reliable glass frit seal, and the relatively high processing temperature.

Patents have been issued over the past several years for various metal-plug-sealed wafer-on-wafer cavity packages. None of these are known to be commercially available at present. In one example, patents describe a method for fabricating a wafer pair with recessed chambers.9 Each chamber has a pluggable vent hole for evacuating gases. After the evacuation of gases from the chamber, the hole is closed with a deposited metal vacuum seal by either evaporation or sputtering of a thick layer of metal. Residual pressures are claimed in the patent to be below 10 mTorr.

A high-vacuum hermetic cavity package has been demonstrated for IR microbolometer packaging and for RF-MEMS switch packaging.10-12 In this method, the cap cavities are evacuated though a vent opening, which is closed by the final solder reflow sealing process. The seal ring solder of each die is deliberately indented to provide cavity venting for evacuation before sealing. Reflow of the evacuated assembly closes the vent with a hermetic solder seal. The BCB-sealed cavity package described above is a near-hermetic modification of this process.

Figure 3. A portion of a cavity wafer, prepared for covalent bonding. After dicing, each cavity will cap a separate chip. Photo courtesy of Ziptronix Inc.
Click here to enlarge image

The process flow includes depositing an under-bump metal (UBM) on both the die and cap wafers before plating the solder for the seal ring. The wafers are plasma treated to permit later fluxless reflow soldering. Assembly is cap on wafer. The cap wafer is diced, and the cap chips are aligned and thermo-compression tack-bonded to the die wafer. The tack bonding holds the caps in alignment during their transfer to the reflow chamber. All of the assemblies are simultaneously reflowed in a vacuum chamber, hermetically solder sealing the evacuated cavities.

The wafer is diced to provide individual devices. RF MEMS relays were the initial test vehicles. The process has since been used for microbolometer infrared sensor arrays, with a germanium window. Microbolometer sensor arrays require maintaining a high vacuum to minimize heat loss. Cavity pressures reported with this process are below 0.01 mb (7.5 ¥ 10-3 Torr).

Table 1. Comparison of wafer-level cavity packages by sealing methods, type of assembly and hermeticity.
Click here to enlarge image

Other techniques used for wafer-on-wafer sealing include anodic, fusion and covalent bonding. High processing temperatures generally limit the applicability of anodic and fusion bonding. In covalent bonding, clean planarized wafers brought into close contact form covalent bonds. A recently announced room-temperature covalent bonding process, currently in development, may be applicable to vacuum cavity bonding.13 Device and cap wafers are planarized and put through a series of surface conditioning treatments. When the treated surfaces are brought into intimate contact, covalent bonds are created, forming a hermetic seal. Figure 3 shows a portion of a cavity wafer prepared for covalent bonding. This specific process applies only to silicon wafers and related materials, such as SiO2 and Si3N4. The process is potentially extensible to vacuum and controlled atmosphere cavities, assuming that the wafer assembly can be completed in a suitable chamber.


Table 1 summarizes the wafer-level cavity approaches described above. Differing market needs have led to a wide range of proposed wafer-level cavity packaging processes. Those needs range from non-hermetic, short-lifetime consumer products to 30-year-lifetime precision instruments. Continuing R&D ranges from extending the technology for higher vacuum nL-packages to defining and measuring acceptable near-hermeticity for shorter-lifetime and lower-cost products. These differing markets will continue to support a spectrum of approaches suited to their needs for size, lifetime, performance and cost.


  1. ShellCase Ltd., www.shellcase.com.
  2. Radant MEMS Inc., www.radantmems.com.
  3. Jourdain, et al., “Investigation of the hermeticity of BCB-sealed cavities for housing RF MEMS Devices,” MEMS 2002 IEEE International Conference, pp.677-80.
  4. T. F. Marinis & J.W. Soucy, “Vacuum packaging of MEMS inertial sensors,” Proc. IMAPS 2003 International Symposium, Boston, MA, Nov. 18-20, 2003, pp 386-391.
  5. B. Farrell et al., “The liquid crystal polymer packaging solution,” Proc. IMAPS 2003 International Symposium, Boston, MA, Nov. 18-20, 2003, pp 18-23.
  6. R. W. Lussignea, “Liquid crystal polymers: new barrier materials for packaging,” Packaging Technology, October 1997.
  7. P. De Moor et al., “Low temperature zero-level hermetic packaging for MEMS based on solder and polymer bonding,” IMAPS 5th Topical Workshop on MEMS, Related Microsystems and Nanopackaging, Boston, MA, Nov. 20-23, 2003.
  8. “SUMICAP Surface micro-machined encapsulation on wafer level,” IMEC, January 2000, www.imec.be/SUMICAP.
  9. R. Higashi et al., US Patent 5,895,233, “Integrated silicon vacuum micropackage for infrared devices,” April, 1999; R. A. Wood et al. US Patent 6,036,872, “Method for making a wafer-pair having sealed chamber.” March 2000.
  10. H. Tilmans, et al., “The indent reflow sealing (IRS) technique—a method for fabrication of sealed cavities for MEMS devices,” Journal of Microelectromechanical Systems, Vol. 2, No. 2, pp. 206-217, June 2000.
  11. P. De Moor et al. “Hermetically sealed on-chip packaging of MEMS devices,” Proceedings of the European Space Components Conference—ESCCON 2000, Noordwijk, The Netherlands, March 21-23, pp. 67-69, 2000.
  12. P. De Moor et al., “Process Development of fast and sensitive polySiGe microbolometer arrays,” In: Photodetectors:Materials and Devices VI., SPIE, 2001. pp 94-100 (Proceedings of SPIE; Vol.4288.).
  13. Ziptronix, Inc. www.ziptronix.com.

GEORGE A. RILEY, founder and owner, may be contacted at FlipChips Dot Com, 210 Park Avenue #300, Worcester, MA 01609; (508) 753-3572; e-mail: griley@flipchips.com.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>



Edwards launches new Smart Thermal Management System at SEMICON Europa 2016
10/25/2016Smart TMS helps semiconductor, flat panel display and solar manufacturers improve their process performance and safety by red...
Tektronix introduces Keithley S540 power semiconductor test system
10/19/2016Tektronix, Inc., a worldwide provider of measurement solutions, today introduced the Keithley S540 Power Semiconductor Test System, a ...
Novel Wafer Analyzer for up to 300mm wafer using high speed Raman Imaging Technology
08/08/2016Nanophoton introduces RAMANdrive - a new Wafer Analyzer - for a wide range of applications at semiconductor market a...