Next-generation Packaging Materials

NEW DEVELOPMENTS IN BOARD/PACKAGE MATERIALS AND PROCESSES

BY RAO TUMMALA, P. MARKONDEYA RAJ AND VENKY SUNDARAM

For the convergent electronic systems of the future with computing, communication, consumer and biomedical functions, it is now widely accepted that a new set of “package” technologies are necessary.

Unlike the packaging technologies of the past, which provided simply wiring either to interconnect transistors or components, the new technologies require the integration of such components as RF, digital, optical and sensing. Emerging packaging technologies, such as system in package (SiP) and 3-D stacking, use discrete active and passive components to achieve higher density through chip or package stacking. System on package (SOP)1-4, a conceptual system technology paradigm that can be thought of as Moore's Law for system integration, is being pioneered at Georgia Tech's Packaging Research Center (PRC), an NSF-funded Engineering Research Center. SOP achieves full system integration by thin film component integration for microminiaturized, multifunction packages.

Future integrated systems packaging like SOP requires a new set of package and board materials with the best combination of thermomechanical and electrical properties. This article reviews recent developments in three key materials, namely package or board materials with high modulus for thin film build-up wiring, package materials with a low coefficient of thermal expansion (CTE) for improved solder joint reliability, and ultra-low loss and thin film low-stress dielectrics for high-speed, density, and reliable wiring.

Emerging Packaging Concepts

Package integration approaches such as SiP, 3-D chip and package stacking and multichip modules have been and are being developed in the industry as an alternative to single chip integration using system on chip (SOC) (Figure 1). SOC presents unparalleled challenges that include long design times resulting from integration complexities, high wafer fabrication costs, test costs and mixed-signal processing complexity requiring dozens of mask steps and IP issues.


Figure 1. SOC, MCM, SiP and SOP.
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SiP is being pursued by several semiconductor and packaging companies worldwide and involves primarily stacking of bare of packaged ICs and, in some cases, uses discrete active and passive components in a single package/module to integrate multiple system functions. Although today's SiP technologies overcome some of the challenges of SOC and has been extended to certain heterogeneous functions, such as microprocessor and memory, SiP has two major limitations. It is a package integration or a sub-system technology and not a complete system technology, and it is limited by what CMOS can perform. While CMOS is great for transistors and certain other components, it is not an optimal platform for certain digital, optical and RF components. This is where SOP comes in with synergy between IC and package. — ICs for transistors and package for ultra-thin film embedding of RF, optical and certain digital components for the convergent and microminiaturized smart electronic and bioelectronic systems of tomorrow.

SOP Paradigm

In the SOP concept the package is the system, not the bulky board. While systems of the past consisted of bulky boxes housing hundreds of components that perform one task such as computing or communications, the SOP concept consists of system functions to include computing, communication, consumer and other functions — all of these functions in a small system package no greater than the size of a Pentium processor package (35 mm in size). The SOP concept makes this possible by ultra-thin film integration of components from current 50 components/cm2 on typical system level boards, to as many as 10,000 components/cm2 with microscale technologies, and more than a million components/cm2 with emerging nanoscale component technologies. SOP can be thought of as Moore's Law for systems by component integration, akin to Moore's Law for transistor integration.


Figure 2. Materials integrated in the SOP concept.
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SOP overcomes the performance limitations of system on chip (SOC), including latency and global delay, RF component integration — while providing a compact platform for integration of digital, RF, optical and MEMS devices. The SOP concept uses the best IC integration of SOC along with best package integration of SiP, 3-D and MCM technologies and component integration of system boards to arrive at an optimized total system solution. The SOP concept seeks to integrate multiple system functions into one compact, lightweight, thin profile, low-cost, high-performance packaged system. This is accomplished by co-design and fabrication of digital, optical, RF and sensor functions in both IC and the package — optimizing functions that are accomplished best at IC level (SOC) and at package level (SiP/3-D). An example of a buildup SOP package with integration of three functions is illustrated in Figure 2.


Figure 3. Digital, RF and optical function integration in one SOP package.
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A typical SOP package has a size of approximately 35 × 35 mm, with about four ICs for analog, digital and optical functions. Similar to a wafer-to-IC concept, the SOP packages will be fabricated on 600 × 600-mm panels using low-cost processes used in high-density organic packages, and then diced — leading to tremendous size and cost reduction, functionality, performance and reliability. The integration of several materials technologies is at the heart of SOP technology for multiple functions. Figure 3 illustrates the various materials used in fabricating SOP packages..These include low CTE, high modulus substrates, high- and low-k dielectrics with ultra-low loss, ultra-fine copper metallization, resistor and inductor thin films, polymer optical waveguides and high-performance underfill materials. This article makes a compelling case for three important materials — package board with ultra-high modulus for multilayer thin film build-up wiring with minimum via capture pads, package/board materials with close to silicon CTE for improved solder joint reliability, and ultra-low loss dielectrics for high-speed, high-density wiring and high-reliability wiring.

Future Board with High Modulus

The latest 2003 ITRS5 roadmap highlights the need for package wiring density to support 100- to 120-µm-pitch area array flip chip by 2007. An area array I/O pitch of 100 µm translates to a 100-µm substrate via pad pitch. The wiring demands for typical SOP packages beyond 2007 will require 5 to 7 signal layers for digital alone, and an additional 2 to 3 layers for RF, and another 2 to 3 optical layers — for a total layer count around 10. The stringent need to process 10 or more layers of thin films, with via sizes of 10 µm and capture pads less than 50 µm, requires substrate materials with warpage in the few microns over 300-mm in size. As shown in Figure 4, via-to-pad misalignment of less than 10 µm requires warpage control to 5 to 10 µm/inch over 300 mm for 0.65-mm-thick substrates.


Figure 4. Substrate warpage control required for future high-density SOP packaging.
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Figure 5 shows the relationship between substrate modulus and process-induced warpage for sequential buildup of 10 layers of 5-µm line/space wiring with 35-µm via pads. Based on thermomechanical modeling, the modulus required for the substrate is in excess of 400 Gpa, represented by the acceptable warpage. The ideal package/board material should not only have high modulus for thin film processing capabilities, but also have large area and low-cost processing capabilities to allow for inexpensive and easy machinability.


Figure 5. Effect of elastic modulus on SOP package substrate warpage.
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Currently, package/board materials like FR-4 and BT do not have sufficient modulus to support multiple layers of thin film processing for SOP packages. Pitch carbon has diamond-like stiffness, and a pitch carbon epoxy can yield a stiffness of 200 Gpa when the reinforcement is more than 60 vol. percent, but the high filler loading results in a brittle composite material. Metal matrix composites possess many attractive properties such as machinability and high thermal conductivity, but do not meet stiffness requirements. Commercially available Al-matrix composites filled with carbon cloth reinforcement do not possess attractive stiffness. Ceramics like AlN and SiC possess just enough stiffness and a CTE close to Si to provide reliability without underfill. Nevertheless, they are not available in large area and need expensive processing.


Figure 6. Area assembly pitch reduction requiring lower CTE boards.
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A manufacturing process (patented by Starfire Systems Inc., NY) has been demonstrated to yield large area, thin, carbon-silicon-carbide-based composite boards with the required stiffness and Si-matched CTE.6 Composite panels of carbon fibers and a silicon carbide matrix are formed from commercially available carbon fiber fabrics and felts and a liquid polymeric ceramic precursor. The polymeric precursor is a highly branched polycarbosilane, which decomposes on firing to 850°C to give amorphous silicon carbide. This pre-ceramic polymer allows design and fabrication of advanced ceramic matrix composites at low temperatures, in large area sheets with tailorable CTE and modulus.

Future Board with Low TCE

The other key property requirement for package substrates is based on solder joint fatigue and flip chip reliability. Current flip chip package solutions for 200-µm-pitch area array use BT resin and high glass transition temperature (Tg) FR-4 laminates with a CTE of 18 ppm/°C (Figure 6). A silicon die has an approximate CTE of 2 to 3 ppm/°C, and thermomechanical stresses are induced in the package from the CTE mismatch between the die, the substrate and the buildup materials. These thermomechanical stresses result in solder joint failure, die cracking, delamination of the solder bumps and cracking of the build-up layers — leading to failure of the assemblies.7 As the chip-to-package interconnect pitch is reduced to 150 µm, the industry is already migrating to laminates with CTE in the 8 to 12 ppm/°C range. For future interconnects at 20- to 100-µm pitch, the solder joint fatigue problem will increase and necessitate the use of package substrate/board materials with CTE in the 3 to 5ppm/°C range close to silicon. Though underfill materials are used to enhance flip chip reliability, they impose several bottlenecks to accomplish high component density, fine pitch and high I/O density. CTE matched substrates have the potential to meet flip chip reliability requirements without underfill materials (Figure 7).


Figure 7. Summary of package/board materials with modulus and CTE.
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Low CTE base boards have been developed and evaluated for increased flip chip reliability by several industry and academic research groups. IBM's glass-ceramic modules can be tailored to have exact CTE match with Si, and show reliability without underfill.8 Low CTE organic laminate materials have also been developed with advanced fillers such as kevlar-aramide, having negative CTE, which results in low net CTE.9,10 DuPont's non-woven aramide-reinforced laminate systems have tunable in-plane CTEs that reduce the CTE mismatch between semiconductors and laminate substrates. This results in reduced strain on solder joints during thermal cycling and a higher-reliability packaging system. These materials also have high laser drillability, thanks to the absence of woven glass fiber reinforcement. Low CTE boards of metal core (invar) also demonstrate better thermomechanical reliability. Laminates from Endicott Interconnect use thin Cu-invar-Cu cores and multilayer PTFE dielectric; they demonstrate reliable flip chip assembly at 180- to 225-µm pitch. Epoxy-based low CTE laminates from Hitachi Chemical also show benefits for fine-pitch flip chip and wafer-level package assembly and reliability.11

Future Package Dielectrics with Low Loss

An integrated SOP package with embedded components and digital, RF and optical functions requires ultra-low loss dielectrics that have stable electrical properties over a wide range of frequency and temperature. Digital signal data rates in the package in excess of 5 Gbps are needed for mixed-signal packages beyond 2007. Voltage levels are also dropping steadily and predicted to be below 1V for 65-nm node ICs. The signal loss and noise levels have to be reduced significantly to meet these specifications. Combined with the low loss requirements for multiple GHz RF signals in the package, there is a critical need for dielectrics with loss tangent ~0.001 and dielectric constant close to 2.0. Thin films of 5 to 10 µm are needed to achieve high-density routing with 3- to 5-µm lines and spaces, while maintaining 50Ω impedance. A summary of commonly used dielectric materials is shown in Figure 8, with respect to loss tangent and film thickness.


Figure 8. Low loss dielectrics and future requirements.
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Epoxy-glass laminate is the lowest-cost material and, consequently, holds a large market share in package substrates and PCBs. FR-4 and other epoxy dielectrics have presented limitations due to higher loss tangent, high CTE, low thermal conductivity and high moisture uptake. Ceramic dielectrics have excellent high-frequency electrical properties, but are traditionally used in thicker films that limit density. Low loss polymers (tan δ < 0.005) such as BCB, polyimide, poylphenyl ether (PPE), teflon, LCP and others, reduce heat generation in the substrate and reduce crosstalk — enabling signal traces to be spaced much closer. These materials have found niche applications, but cost is crucial for widespread acceptance of a material. Several low loss dielectrics have been characterized and used in high-speed and high-frequency packages and PCBs around the world. An example of eye opening measurements and the effect of dielectric loss is illustrated in Figure 9. The ideal dielectric material for future high-performance applications should combine PTFE-like electrical properties with thin film capability and ease of processing.


Figure 9. Eye opening measurements for low loss dielectrics at 5 Gbps data rate.
Click here to enlarge image

While the electrical properties dictate that low loss dielectrics like BCB are needed for high-frequency and high-speed applications, thermomechanical properties also need to be considered for proper selection of the dielectric materials on low CTE boards. The new low CTE boards come with the penalty of additional issues in dielectric reliability. Modeling results show that although the Si-matched CTE of board produces low solder joint fatigue, it increases the stresses in the dielectric. Predicted dielectric stresses on FR-4 boards are approximately 30 MPa, while the dielectric stresses on low CTE boards can be as high as 55 MPa. Apart from dielectric CTE and strength, the thickness of the buildup dielectric layer is also a vital factor in deciding dielectric reliability. Negligible dielectric cracking has been observed with thinner buildup of BCB or PPE (30 µm), compared to thicker epoxy buildup (80 µm) on low CTE boards.

Resin-coated foils (RCF) are popular for buildup microvia substrates. RCFs with varying resin types and different material properties are being developed and evaluated by Hitachi Chemical Co.12 These dielectrics have CTEs as low as 11 ppm/°C, with stiffness of 1 GPa without any filler. Inorganic fillers are also incorporated to yield high-stiffness, low CTE RCFs. Polynorbornene-based dielectrics, with inherently low stiffness (< 1 GPa) and excellent dielectric properties and thermal stability, also show tremendous potential. Low CTE polyimides (HD Microsystems) with coefficient of expansion of 3 ppm/°C show nearly zero residual stress in the dielectrics and minimal warpage. BCB and PPE buildup on low CTE C-SiC boards show no failures until 1,000 cycles. The ideal dielectric should have high strength and toughness (elongation to failure), and low CTE and low modulus.

Conclusion

With the trend in convergent systems and functions with digital, RF, optical and MEMS in a single package or module, a new set of package material technologies are necessary. Fine-pitch (20 to 100 µm) area array interconnections are driving the need for package/board materials with CTE in the 3 to 5ppm/°C range for improving solder joint reliability and modulus greater than 400 GPa for up to 10-layer buildup wiring with minimum via capture pads. Electrical performance to signal speeds in excess of 5-10 Gbps in the package drives the need for ultra-low loss dielectric materials. The dielectric materials also should have low CTE, high strength and must be processable into 5- to 10-µm thin films. A number of new substrate and dielectric materials with improved electrical and thermomechanical properties are being developed around the world for large area manufacturing. The PRC is exploring high modulus, low CTE C-SiC composite substrates, along with thin film dielectrics such as BCB with 5-µm lines/spaces and 15- to 20-µm microvias as a potential solution for high-density substrates for SOP packaging beginning around 2007.

ACKNOWLEDGEMENT

The authors would like to thank all of the PRC faculty, research staff, and students who contributed to this work. Special thanks to Steve Atmur, Dr. Susan Hayes and colleagues at Starfire Systems, Malta, NY, for collaboration on C-SiC substrates. This work was supported by the National Science Foundation through the Georgia Institute of Technology/NSF Engineering Research Center in Electronic Packaging (EEC-9402723) and the National Institute of Standards and Technology — Advanced Technology Program (NIST-ATP).

REFERENCES

  1. R. Tummala, “SOP: Microelectronic Systems Packaging Technology for the 21st Century,” Advancing Microelectronics, Vol. 26, Issue 3, May-June 1999, pp. 29-37.
  2. R. Tummala, J. Laskar, “Gigabit Wireless: System-on-a-Package Technology,” Proceedings of IEEE, Vol. 92, Issue 2, February 2004, pp. 376-387.
  3. R. Tummala, V.K. Madisetti, “System on Chip or System on Package? Design and Test of Computers,” IEEE, Vol. 16, Issue 2, April-June, pp. 48-56.
  4. R. Tummala, “SOP: What is it and Why? A New Paradigm for Miniaturized Convergent Systems of the Next Decade,” IEEE Transactions on Advanced Packaging, June 2004.
  5. “Assembly and Packaging”, International Technology Roadmap for Semiconductors, 2003 Edition.
  6. Starfire Systems Inc., Malta, NY, www.starfiresystems.com.
  7. R. V. Pucha, S. K. Sitaraman, S. Hegde, M. Damani, C. P. Wong, J. Qu, Z. Zhang, P. Markondeya Raj and R. Tummala, “Materials and mechanics challenges in SOP-based convergent systems,” Invited paper, Special issue on micromaterials and nanomaterials (to Andreas Schubert in memorium), IEEE Components Packaging Manufacturing Technolgy Transactions, 2003.
  8. R. Tummala, E.J. Rymaszewski and A.G. Klopfenstein, “Microelectronic Packaging Handbook,” Edited, International Thompson Publishing, Vol. 2, 2nd Edition, New York, NY, 1997.
  9. S, Khan, C. G. Gonzalez and M. Weinhold, “Organic, Non-woven Aramid Reinforced Substrates with Controlled In-Plane CTE Means More Reliable Solder Joint Reliability,” Advances in Electronic Packaging, Vol. 2, 2001, p 1345-1362.
  10. T. S. Krziwanek, “Low CTE materials for Printed Wiring Boards,” pp. 175-180, Proceedings, International Symposium & Exhibition on Advanced Packaging Materials International Microelectronics and Packaging Society, 2001.
  11. K. Nakamura, M. Kaneto, Y. Inoue, T. Okeyui, K. Miyake, S. Oota, “Multilayer Board with Low Coefficient of Thermal Expansion,” Proceedings 33rd International Symposium on Microelectronics, International Microelectronics and Packaging Society, 2000, pp. 235-240.
  12. Atsushi Takahashi, Kazuhito Kobayashi, Shigeharu Arike, Norio Okano, Hajime Nakayama, Akihiko Wakahayashi, Takayuki Suzuki, “High Density Substrate for Semiconductor Packages Using Newly Developed Low CTE Build Up Materials,” International Symposium on Advanced Packaging Materials, 2000, pp. 216-220.

RAO TUMMALA, P. MARKONDEYA RAJ AND VENKY SUNDARAM may be contacted at Georgia Institute of Technology, Packaging Research Center, 813 Ferst Drive, NW, Atlanta, GA 30332-0560; e-mail: rao.tummala@ece.gatech.edu, raj@ece.gatech.edu, vsunda@ece.gatech.edu.

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