Packaging Alternatives



Interest in system-in-package (SiP) and system-on-package (SOP) technologies is increasing. The package design typically is one single flip chip die with a few chip scale packaged DRAM or SRAM and multiple decoupling capacitors. This packaging concept is a compromise between a single chip ball grid array (BGA) mounted on a PCB and a full multichip module where all devices are flipped.

Click here to enlarge image

The SiP/SOP design approach allows two advantages. First, it enables an electrical improvement in performance because it eliminates the connections from the ASIC, FPGA or microprocessor, through package connection, PCB and another set of connections to memory. Each of these connects becomes a potential reflectance at high bandwidths. This approach also reduces conductor lengths, further reducing inductance. The second advantage is a reduction in PCB cost. For instance, sweeping the memory devices onto the same package surface with an ASIC allows fewer connections between package and PCB. This reduction in PCB printed through holes (PTHs), wiring and SMT pads enables a reduction in PCB layers. An apparent enabler of this design approach is the availability and quality of memory devices using chip scale packages (CSPs). The CSP is a testable packaged die, so the concern with known good die is eliminated.

Package reliability, especially when using flip chip assembly, continues to be a concern. In the past, multichip approaches were dominated by multilayer ceramic chip packages. Recently, plastic packages have emerged in this application space because they are expected to be more cost effective. But plastic combined with flip chip assembly has raised reliability concerns — especially in joints between die and package.

Reliability Performance

The reliability of packages used in either single or multichip applications has as many potential failure modes, and these can be simplified into three main failure locations. These are failures at the flip chip connections, package-to-board connections and within the packages. This article considers the flip chip attach and BGA connections being used in these multichip applications. These failures are caused by mechanically coupling dissimilar materials. A CTE mismatch between materials presents serious reliability concerns at both flip chip and BGA locations if the discrepancies are large.

For example, in a ceramic flip chip the mismatch from mechanical coupling between silicon with a CTE of 3.0 ppm/°C and a typical alumina ceramic package with 6.5 ppm/°C is 3.5 ppm/°C. The material mismatch is relatively low, so the reliability of the flip chip joint is at low risk. But on the opposite side of the package, connections can be ball grids to the PCB. The mismatch between the ceramic and PCB at 16 to 18 ppm/°C is much larger. The BGA joint in this case is a large reliability concern, especially with package body sizes above 33 mm. This concern grows with increasing distance from the neutral point that corresponds to increasing package body size. Ceramic applications use column grid arrays to act as bending beams for compensation. But columns are large inductors compared to BGAs, and have a lower electrical performance at higher bandwidths. Another connection technique used in many ceramic applications is land grid array. A land grid array on the package side connects to a socket assembled to the PCB. The socket and socket assembly are costly, and this connection is usually electrically inferior to a BGA connection.

Figure 1. This component cross section shows die and bump.
Click here to enlarge image

Standard plastic flip chip packages, such as buildup, have the opposite issue. They are matched well to the PCB (CTE = 15 to 18 ppm/°C), but there is significant mismatch between die and package. This problem increases as the distance to the neutral point increases. Increasing die size presents itself in a similar fashion as increasing body size. Warpage in the die site during assembly is an additional problem typically stemming from CTE mismatch when using a plastic flip chip package. This can result in high stress placed on the flip chip connections, but can also result in die cracking.

Although the multichip package approach can reduce PCB costs and improve electrical performance, confounding these improvements with reliability concerns could eliminate any cost advantage of using this solution. The solution should be in finding a package that enables a reliable multichip package approach. This package would also need to eliminate any reliability concerns within the package itself.

A PTFE-based plastic package*, developed by one company**, has demonstrated reliability at both the die and PCB interconnects with flip chip and BGAs. This package uses a low stress, PTFE-based dielectric that provides better electrical characteristics compared to ceramics, as well as typical buildup flip chip plastic packages. The electrical performance is attributed in part to the low dielectric constant and low dielectric loss of this PTFE material. Reliability of the package is provided by combining the highly compliant, low stress PTFE with a copper-invar-copper (CIC) core material that also serves as a ground plane. But the main purpose of the CIC is to provide thermal expansion compensation to the PTFE dielectric.

Comprehensive reliability testing of the new package has been conducted for large semiconductors up to 18.3 mm, and large package body sizes up to 52.5 mm. Testing was designed to simulate field conditions, so heat sinks were attached to the component after assembly to a PCB. Table 1 shows the testing performed on the new package with an 18.3-mm die with high melt bumps, assembled to a 2,577 I/O, 52.5-mm with an 89 × 104-mm aluminum heat sink that weighed 200 g.

Table 1. Reliability performance.
Click here to enlarge image

A picture of the assembly is shown in Figure 2 that shows the package beneath a 200-g heat sink. The test PCB was depopulated in three BGA sites to allow the viewer to judge the size difference between the package and heat sink. The body size outline is basically the outline of the BGA pads on the PCB.

Figure 2. This image shows the new assembly beneath a 200-g heat sink.
Click here to enlarge image

Although this is a single chip component, it proves that large die can be attached to a plastic package and display high-performance reliability. The new package was designed and tested with ceramic flip chip capacitors. Since the results shown are for both packaged die and capacitors, this confirms the reliability claim that the technology can support multiple components. Figure 3 shows the bottom of the tested package, with the full array matrix of the BGA and below it and the exposed die site and five capacitor sites.

Figure 3. The bottom of the tested package shows the full array matrix of the BGA and below, as well as exposed die and capacitor sites.
Click here to enlarge image

The new single-chip package normally has a stainless steel stiffener surrounding the die and capacitors. The role of the stiffener is to ensure die site flatness during die attach, and package coplanarity during second-level assembly.

Technology Platform

Since the reliability test results were positive, use of this technology as a platform for other package types provides the industry with a viable alternative. The data supports flip chip and less dense attach processes such as CSPs. With the reliability concern minimized, package designs like this have begun to replace ceramic packages.

Figure 4 shows an assembly tray loaded with 12 multichip packages using the new package. The package description is a single-chip FPGA flip chip assembled in the center of a 39 × 55-mm BGA. The four dark rectangles in the corners are SRAMs packaged in a 0.8-mm CSP. There are 10 capacitors mounted along the package edge, although smaller decoupling capacitors can be mounted closer to the die. The package-to-PCB connection uses BGAs, but other connection types are compatible with this solution.

Figure 4. This image shows an assembly tray loaded with 12 multichip packages using the new technology.
Click here to enlarge image

No stiffener is attached to the substrate prior to die attach. Once die and SMT components are attached, a heatspreader (that also acts as a stiffener) is commonly assembled to the package. The heatspreader can be in either one or two pieces, although two pieces seems to be more cost effective. One piece is a rectangle window frame that surrounds the outside edge of the package. The second is multi-tiered to compensate for the different heights of the die, CSPs and capacitors. The outline of the second piece matches the outline of the picture frame, which allows the heatspreader to provide stiffness to the package.


The market continues to evolve and use new packaging types and techniques to keep pace with semiconductor advances. From the wide base of packaging offerings, it is evident that no one solution is the best for every application. For OEMs searching for alternatives to single-chip packaging, the concept of producing a functional island as a SOP is a desirable solution, as long as the package does not introduce reliability issues. Careful consideration should be given to the type of substrate used to package the system — especially if flip chip is used for die attach. Organic substrates provide a viable solution to packaging multiple die on a single package.

** Endicott Interconnect Technologies Inc.

KIM BLACKWELL, product manager of Semiconductor Packaging, and KAREN CARPENTER, director of Marketing and Communications, may be contacted at Endicott Interconnect Technologies Inc., 1701 North Street, Endicott, NY 13760; (670) 755-2843; e-mail: and karen.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>


Entegris announces GateKeeper GPS platform
07/15/2014Entegris, Inc., announced last week the launch of GateKeeper GPS, its next-generation of automated regeneration gas purification system (GPS) technology....
Bruker introduces Inspire nanoscale chemical mapping system
07/15/2014Bruker today announced the release of Inspire, the first integrated scanning probe microscopy (SPM) infrared system for 10-nanometer spatial...
MEMS wafer inspection system from Sonoscan
06/25/2014Sonoscan has announced its AW322 200 fully automated system for ultrasonic inspection of MEMS wafers....