BY MARCOS KARNEZOS
Wireless applications such as cell phones and consumer products like pocket PCs require maximum functional integration in the smallest footprint, lowest profile and low-cost packaging. Stacked-die chip scale packages (CSPs) integrate an ASIC and memories such as flash, SRAM and DDR into one package by stacking probed good die, interconnecting them with wire bonding and molding all into one JEDEC-standard package. They provide the smallest footprint and lowest profile compared to 3-D stacked packages. They also have the lowest packaging cost compared to individually packaged die or other 3-D packages, but low cost of ownership requires good die. One bad die will ruin the entire module, and rework is not an option. Known good die (KGD) are desirable, but are as expensive as packaged die and not widely available. Therefore, probed good die in wafer form is the established supply chain for stacked-die packaging.
Stacked-die packages in high-volume production are assembled using the established infrastructure of materials, equipment and processes used for conventional one-die CSPs and tested with the same handlers and testers. More than one tester may be necessary. They meet the same reliability standards at the package and board level and are offered with lead-free and “green” materials.
Figure 1. Stacked-die packaging roadmap.
The major challenge to the packaging industry is stacking more dice in a thinner package (Figure 1). More dice require a denser substrate, a more complex interconnect and more elaborate test. A thinner package needs all the layers to be thinner, which require some new materials, more flexible and precise equipment, and assembly processes that are stretched to their limits, requiring much better control.
Stacked-die CSP Example
The majority of applications are stacked memory, including Flash (NOR/NAND), SRAM or DDT, and more recently, an ASIC. A typical memory-stack package is a CSP with a 10 × 12-mm body, 1.4-mm thickness and a 145 ball count at 0.8-mm pitch. An equivalent package that contains an ASIC plus memory has a 15 × 15-mm body size at the same 1.4-mm thickness, but >500 ball count at 0.5-mm pitch. Figure 2 shows a stack of four dice with two spacers. The technologies used in producing such a package include wafer thinning, thin wafer sawing, multiple die stacking, spacer technology, wire bonding on overhanging die, very low loop height, long wire bonding, die-to-die bonding, very thin mold cap technology, very thin and dense substrates, fine-pitch solder ball assembly, and, of course, an integrated design, performance (thermal, electrical, mechanical) modeling and simulation supported by measurement and failure analysis capability.
Wafer Thinning and Sawing
All stacked-die packages require wafer thinning. The package shown in Figure 2 uses 200-mm wa-fers thinned down to 75 µm. Thin wafers left un-supported will bow and curl up under the stress of the numerous thin-film layers of the circuit and the thick passivation layer. Wafer thinning in-line supports wafers on tape for better process control and minimum breakage from handling. It includes a two-step back grind process, a rough and then fine grind, followed by a mechanical polishing that removes about 2 µm of damaged silicon and the associated stress. Furthermore, the same in-line system can attach a thin 20-µm die attach film from a roll to the back of the wafer before mounting on the saw tape.
Figure 2. Stacked-die package with four die and two spacers.
Sawing of thin wafers is more prone to silicon chipping and pad metal peel, particularly with 300-mm wafers and multilayer copper interconnect and low-k dielectrics. A two-step cut process or laser cutting is recommended for a smooth edge below 100-µm-thick wafers. Thin and large die can warp after sawing to the point that the following steps of die pick and die attach may need special attention.
Die Attach and Spacer Technology
Thin die are flexible, and the conventional die-pick and die-attach tools need to be modified to support the die uniformly, avoid bending and ensure uniform die- attach layer thickness when paste is used. Tape die attach is preferred for 100-µm and thinner die to achieve a thin die- attach layer, better bond line thickness uniformity and good adhesion without voids. Paste is recommended for the bottom die to fill the uneven substrate surface and prevent voids.
Stacking of chips with varying die sizes requires a spacer between the die when the top die is either the same size or larger than the bottom to avoid damage to its wires. Numerous spacer materials have been used, including silicon, adhesive paste with large spacer spheres or thick tape. Each presents different advantages and shortcomings. Silicon is widely used because it fits the infrastructure and is cost effective, but it has more processing steps. Epoxy with spacer spheres requires fewer process steps, but has more epoxy bleed. Tape has no bleeding, but is more costly. Epoxy with spacer spheres is preferred for <100-µm-thick die, because it minimizes the overhanging span of the top of the die and enables wire bonding.
Wire Bonding: Overhang, Low Loop, Multirow
Wire bonding is the preferred interconnection method in stacked-die packaging. It enables connection of the stacked die to the substrate or die-to-die using the same technology.
Low loop height is critical to achieving low profile packages. On any top die, the loop top must clear the mold cap and leave enough clearance for the laser marking depth. On any bottom die with a spacer on top of it, the loop top must clear the die above and thus defines the spacer thickness. Low looping down to 50 µm is achieved by reverse or forward bonding with folded looping. Reverse bonding first places a gold ball on the die pad or substrate finger, and then does the stitch bond on top of it. The two operations reduce the throughput of the wire bonder compared to the forward bonding that requires one operation. Forward bonding with folded looping attaches the wire directly on top of the ball in one operation and has almost the same throughput as conventional wire bonding, but is available only with the latest wire bonders. Die-to-die bonding is accomplished with reverse bonding, which uses the same pad design rules as forward bonding. In applications where the top die has center pads such as a DDR memory chip, a combination of reverse bonding with long wires in excess of 4 mm is needed. On some occasions, a thicker wire is used to minimize the wire sweep and avoid wire shorting.
Low looping requires a thin, soft, pure gold wire. The intermetallics of the aluminum pad with pure gold are different compared to conventional gold alloy wires. Bond reliability should be tested after molding to include the effect of the molding compound choice.
The sizes of the stacked die are numerous and the industry has developed techniques that practically stack any die combination. In the obvious pyramid stack, where each die is fully supported by the bottom die, wire bonding in either forward or reverse mode presents no particular challenge. When the dice are crossed like memory chips with pads on two sides only, or when the top die is larger than the bottom, a significant die overhang of up to 2 mm can result. Thin die <100 µm bend significantly under the force of the wire bond capillary. Al-though die breakage is not an issue, quality of the ball bond can be compromised if bond parameters such as force and ultrasonic energy are not optimized. This problem can be more challenging when reverse bonding on die with low-k di-electrics that are usually soft and have low shear strength. High-volume bonding on 100-µm-thick die with 1.0-mm overhang is achieved with the latest bonders. Additional wire bonder parameter tuning is needed for designs with circuit under pad (CUP), where multilayer circuit structures are located under the pad for die space savings and cost reduction.
High-performance, high pin count app-lications use in-line, 40-µm pitch with 20-µm wire or three-row staggered wire bonding with 60-µm pitch per row, resulting in 20-µm effective pitch and up to five loop heights on multirow bond fingers. In either case, fine pitch and thin wire are susceptible to significant wire sweep — particularly for long wires >4 mm.
Molding, Top Center Mold Gate
Conventional bottom-gate molding cau-ses 10 percent wire sweep and wire shorts with 20-µm wire at 40-µm pitch. A newly developed top center mold gate (TCMG) provides a uniform and radial mold compound flow from a top gate that minimizes wire sweep to approximately 1%. TCMG requires a smaller clearance from the top die, allowing a thinner package and reduces substrate cost by reducing the overhead space between units on the strip because of the absence of the bottom gold gate. TCMG is critical to molding molcaps <300 µm for both stacked-die and stacked packages. Thin packages are prone to warpage, and chips with low-k dielectrics are more sensitive to stress. In both cases, low modulus molding compounds are proven to minimize the problems.
Thin Core Substrates and Fine Ball Pitch
Thin packages require thin substrates, and most stacked-die applications need multilayer substrates. The majority of packages use 210-µm-thick two-layer laminates with a 100-µm core. Stacks with four to six die, or stacked packages with a 1.4-mm profile, require a 130-µm substrate 60-µm core. Copper polyimide tape is thinner, but one metal layer is not adequate for routing and two-metal layer tape is costly and not widely available. Complex die stacks with high pad count require four-layer substrates for routability, yet the thickness has to be kept at 240 µm to fit the fixed profile.
Solder balls continue to migrate to a finer pitch, but still contribute a significant percentage to the package profile. At 0.5-mm ball pitch, the collapsed solder ball height is 210 µm. At the emerging 0.4-mm pitch, the height is 180 µm.
Shrinking pitch reduces ball diameter and board level reliability (BLR) under thermal cycling, and the more important drop shock test required by wireless applications. Furthermore, BLR is degraded by the Ni plating on the substrate and Au/Sn intermetallics formed at the joint of the solder ball on the Au-plated substrate. Copper organic solderability protection (COSP), rather than Ni/Au plating on the ball pads, is emerging as an attractive option with better BLR. COSP, though well established in the SMT environment, has difficulty surviving the more severe high-temperature package assembly processes. On the bright side, lead-free SnAgCu solder alloys have shown 2× better board-level reliability compared to eutectic solder and are gaining acceptance in consumer products. In anticipation of the industry conversion to lead-free and green materials, and particularly for consumer products, all stacked-die CSPs are being qualified with the newer regulation-compliant materials that pass the same tests as conventional packages. The industry has shown that the ball pick-and-place technology can be extended to at least 0.4-mm pitch, and probably lower though solder paste printing techniques may offer cost advantages if proven to work in high volume.
Design, Modeling, Performance Test
Stacked-die packages have more complicated net lists that must be routed, as well as a heat source in each die that can affect the temperature of the die above and below, have more nested wires that can interfere electrically, and have most of the volume in the package occupied by laminated silicon die that govern the mechanical properties of the package, as opposed to molding compound in conventional packages. Applications driving stacked-die packaging have narrow market windows and are cost sensitive — requiring short time-to-market and low non-recurring expenses. Package design done in conjunction with modeling and simulation of electrical, thermal and mechanical performance will ensure that the design works from the first try without costly and time-consuming redesigns. It is important to view the modeling and simulation as part of the iterative design process done in real time, as opposed to the common practice of verifying performance after the design is completed.
Stacked-die packaging offers functional integration in a minimum footprint, with low profile, low cost and fast time-to-market by using the established packaging and chip supply infrastructure. Package assembly, though more complex than one-die package, has high yields in the 97 to 98% range, and the packaging cost is fractionally higher compared to the one-die case.
The industry is challenged to produce ever-thinner packages with more stacked die from more suppliers. Success in package-level system integration requires a broad set of assembly technologies and close collaboration among all of the stakeholders, including device manufacturers and OEMs.
MARCOS KARNEZOS, chief technology officer, may be contacted at ChipPAC Inc., 47400 Kato Road, Fremont, CA 94538; e-mail: firstname.lastname@example.org.