Wire Bonding Tutorial

Advances in Bonding Technology


Chip-to-substrate interconnections provide the electrical paths for power and signal distribution. The most common interconnect technology is wire bonding, specifically ball bonding. Although flip chip applications are growing, ball bonding continues to produce the vast majority of interconnects. Currently responsible for more than 90% of today’s chip interconnects, ball bonding continues to grow at a phenomenal rate.

The Ball Bonding Process

Ball bonding is the process in which pads are connected onto a die and leadframe (or substrate) using very fine diameter wire. The basic steps of ball bonding include the formation of: the first bond (normally on the chip), the wire loop, and the second bond (normally on the substrate). The wire-bonding cycle is shown in Figure 1.

Figure 1. Ball bonding steps.
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At the beginning of the wire cycle, the bonding tool travels down to the first bond location (Steps 1 and 2). The first bond is achieved by bonding a spherical ball to the pad using thermal and ultrasonic energy (Step 3). The initial bond is also referred to as the ball bond. Looping motions are programmed to meet the package requirement for loop height and shape (Steps 4, 5, and 6).

The second bond consists of a stitch bond that bonds the opposite end of the wire and a tail bond (Step 7). The tail bond is needed to form a wire tail for the next ball formation. After the bonding tool rises to pay out the wire tail, the tail is broken off and the bonding tool rises up to the ball formation height (Steps 8, 9, and 10). The ball formation process is achieved by ionization of the air gap in a process called “electronic flame-off” (EFO). The resulting ball is known as a “free air ball” (FAB).

Wire Bonding Material

Wire bonding materials used in a ball bonding process mainly include the bonding wire and bonding tool. Ball bonding tools are called capillaries, which are axial-symmetric ceramic tools with vertical feed holes. Figure 2 shows an example of a capillary used in fine-pitch applications. The tool’s tip is shaped to give the clearance needed in fine-pitch bonding.

Figure 2. Wire bonding tools.
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Figure 3 outlines the critical dimensions of a capillary, which include the tip diameter (T), angle of the bottom face (FA), outside radius (OR), hole diameter (H), and chamfer diameter (CD). The tip usually is determined by an application’s pitch. FA and OR affect mainly second bond, while the hole and chamfer diameters affect both the first and tail bond formations. These are the most critical dimensions of a capillary.

Figure 3. Critical capillary dimensions.
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Most bonding wire used in ball bonding is gold (Au) wire of 99.99% purity, which is often referred to as 4Ns wire. Alloy wires (99.99% or less purity) are sometimes used to meet special application requirements, such as high wire strength. Studies have shown that certain dopant (impurity in the wire) can slow Au-Al intermetallic growth. 3Ns and 2Ns wires are sometimes considered to improve device reliability.

A special consideration for bonding wire is its heat-affected zone length, which is related to the recrystallization process due to the heat from EFO. The heat-affect zone often weakens the wire. A longer heat-affect zone in the wire often results in higher loop height. Some low-loop applications require high strength and a low heat-affected zone, as shown in Figure 4.

Figure 4. Certain high-strength wire offers shorter heat-affected zone (HAZ) and improved looping capability.
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Copper (Cu) wires can be bonded with some modifications to the wire bonder. The modifications mainly consist of using a forming gas environment to prevent Cu oxidation during the free air ball formation. Both Au and Cu bonding are done at an elevated temperature (normally 150˚ to 240˚C, depending on the device). This process is called thermosonic bonding because of the use of heat and ultrasonic energy.

Wire Bonding Process

The critical steps in the wire bonding process include achieving reliable bonds (first bond, second bond, and tail bonds), maintaining desired loops, and positioning the bonds accurately. Throughput also is an important factor, since it affects the cost of the device.

Achieving desired first and second bonds usually requires optimizing bonding parameters. A design of experiment (DOE) can be done to optimize these parameters, which would include impact force, bonding force, and ultrasonic energy levels. A proper free air ball size normally is determined before starting a first-bond DOE. Looping trajectories are selected according to the application requirements. There are two basic types of loops: forward and reverse. A forward looping process places a ball bond on the die first, then places a stitch bond on the lead, as shown in Figure 1. A reverse ball bonding process, however, places a bump on the die pad first. After the bump is formed, a ball bond is placed on the substrate, followed by a stitch bond on the bump (Figure 5). Low-profile looping requirements have propelled the growing use of reverse ball bonding, which is a slower process than forward bonding.

Figure 5. Forward ball bonding loops in stacked die applications.
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Leading Wire Bonding Applications

The most advanced wire bonding applications include: ultra-fine pitch (<60-µm pitch), stacked die, and multi-tier applications. These advanced applications often require more process optimization, as well as higher requirements for bonding material and equipment.

Fine-pitch Applications. Wire bonding fine-pitch capability has been demonstrated in the laboratory at 35-µm inline pitch. For 35-µm pitch ball bonding, 15-µm wire typically is used with a bonded ball diameter of 27 µm.

Fine-pitch applications demand a higher capability of the wire bonder, including better control of the bonding force, ultrasonic energy level, as well as a looping capability of fine wires, which has much less strength and is more inclined to loop sway. A wire bonder that meets the demands of fine pitch should also include high-precision motion and a vision system with submicron accuracy.

Stacked Die Applications. Stacked die applications are one of the fastest-growing trends in the semiconductor industry. The desire for smaller, lighter, and smarter devices is driving this 3-D packaging technology. Stacked die applications present various wire bonding challenges, including low-loop and multi-level wire bonding loop clearance requirements, bonding to overhang unsupported die edges, and loop resistance to wire sweep during molding.

Most wire bonding applications use the typical forward bonding process, because it is faster and more capable of finer pitch than reverse bonding. However, forward ball bonding has a loop height constraint due to the neck area above the ball. Excessive bending above the ball can cause neck cracks, which results in reliability problems. Reverse bonding can achieve loop height lower than 75 µm (Figure 6).

Figure 6. Reverse ball bonding loops.
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Multi-tiered ICs. Traditional wire-bonded ICs have in-line bond pads on the periphery of the die. In the past, staggered pad designs (2-tier) were commonly used when I/O requirements exceeded silicon real estate. Increasing the number of pad rows (or tiers) is a natural progression in increasing the number of I/Os. Often found with high-end graphic and chip-set applications, tri-tier devices also are becoming more common. Early qualification of quad-tier devices are also beginning (Figure 7).

Figure 7. Multi-tier application.
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Looping is the obvious challenge for the wire bonding process with multi-tiered IC applications. While in-line applications have single layers of loops over the first bond, multi-tiered devices require multiple layers of wire loops – ultimately driving up the overall package height. Loop heights can be as low as 50 to 75 µm for the shortest wires to more than 400 µm on the longest signal wires. In production today, gaps of 2 to 4 times the wire diameter are typical (with larger gaps in the upper layers) to ensure acceptable process yields across a population of wire bonders.

A second challenge for multi-tiered devices is associated with the first bond process. Adding bond pads without increasing the silicon area requires placement of active circuits below the bond pads. This, along with inclusion of low-k interlayer dielectrics, will continue to challenge the first bond process. To bond to this type of package, the wire bonder needs fine control of impact and steady-state bond forces, along with careful control over USG applications.


Wire bonding offers some major advantages, including a large existing infrastructure, programming flexibility, and low cost. Continuing advances in wire bonding technology with increased process integration will enable this process to continue meeting the majority of semiconductor interconnect requirements for many years to come.

IVY WEI QIN, Ph.D., manager, Process Engineering, may be contacted at Kulicke & Soffa, 2101 Blair Mill Road, Willow Grove, PA 19090; 215/784-6000; e-mail: iqin@kns.com.


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