Startup Invarium debuts 65-45nm IC layout tool

February 8, 2006 – Invarium Inc., San Jose, CA, has introduced a new product that it claims is superior to current RET and OPC tools for patterning IC layouts of 65nm- and below chipmaking processes, with an eye toward 32nm and EUV lithography.

The DimensionPPC technology, dubbed “process and proximity compensation” (PPC), offers post-etch critical dimension (CD) uniformity and accuracy, with expanded process windows for any chip layout that is patterned using that fab process, the company claims.

Its “patterning-process-centric” approach includes an analytical model of the entire patterning process to capture key process effects and variations, enabling an accurate simulation of an IC layout patterned post-etch and across the process window. An advanced mask layout synthesis engine is synthesized in one step embodying RETs and inversions of actual process effects, to ultimately produce a mask that delivers the best patterning results on silicon.

DimensionPPC, which runs on standard computer clusters and distributed processors, was fab-validated at 65nm during 4Q05; it’s now in production at one semiconductor manufacturer and is being qualified by five others.

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