TSMC: Immersion yields, defect rates are ramp-ready

February 22, 2006 – Top foundry Taiwan Semiconductor Manufacturing Co. (TSMC) says it’s achieved near-zero defect rates with test wafers using immersion lithography, comparable to dry lithography results and well within acceptable parameters for volume manufacturing.

Defects associated with immersion include microbubbles, watermarks, particles, particle-induced printing defects, and resist residue. Burn Lin, senior director of TSMC’s micropatterning division, claims the company has produced multiple test wafers with defect rates as low as three per wafer, according to . Using a proprietary technique, TSMC reports tests with defect density of 0.014/sq. cm (less than seven immersion-induced defects per wafer), and some wafers yielding defect density as low as 0.006 sq. cm (three per wafer). By comparison, prototype immersion scanners without the proprietary technique can produce several hundred thousand defects.

“With defect root causes understood, TSMC can now focus on throughput improvement for high-volume manufacturing,” stated Lin.

TSMC is planning to utilize immersion lithography for its 45nm process technologies.


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