Examining litho progress, prospects at SEMICON West

by M. David Levenson, Senior Editor

At a SEMI/Dataquest cosponsored event prior to SEMICON West, Klaus Rinnen of Gartner/Dataquest reported a bright outlook for 2006, both for the semiconductor industry (11% growth) and its equipment suppliers (24%), followed by a potential “soft patch” in 2007, before an upturn to record levels in 2008. That feeling of comfort combined with tempered optimism characterized the entire atmosphere at SEMICON West — everyone seemed to feel that things were good now, and that the future is no more uncertain than usual, in our cyclical industries.

The keynote presenter at the SEMI/Dataquest Market Symposium, Wally Rhines, CEO of Mentor Graphics, emphasized the critical role of manufacturing simulation in electronic design. He explained that the ITRS-desired CD uniformity for 45nm generation gates is 4-atom widths, a precision that requires successful designs to incorporate manufacturing realities. Numerous companies, however, are providing the necessary software, including Mentor and >20 startups that have absorbed >$90M of venture capital funding, he reported. Without DFM, chip yield is problematic, according to Rhines, but the necessary models incorporating foundry process data are becoming available. Simulation also facilitates targeting of key structures for in-line metrology, speeding that process, and enables rational discussion about trade-offs involving timing, power, and process window.

The leading edge of lithography in 2006 is the 45nm generation, which everyone seems to expect will be made using 193nm excimer laser exposure with water immersion scanners having numerical apertures near 1.3. Such tools require exceptional laser stability. Enter Cymer, which announced a new model, the 60W XLR 500i, incorporating an innovative “ring” power amplifier. In such a system, the light injected from the master oscillator circulates through the amplifier chamber until it extracts all the available energy, rather than exiting after one or two passes. Near complete energy extraction improves pulse energy stability by 50%, reported Nigel Farrar, VP of lithography applications marketing at Cymer. Stability reduces the number of pulses needed to land in a narrow exposure window, facilitating increased scan speed and throughput. Ring technology also permits reducing the master oscillator energy, which improves component lifetime and reduces cost-of-ownership (CoO), according to Farrar.

Industry leaders discussed the prospects for 32nm half-pitch lithography at a breakfast presentation sponsored by Sokudo Corp., the new DNS/Applied Materials joint venture in coat-development tracks. Keynote speaker Burn Lin of TSMC pointed out that logic will not truly require a 32nm half-pitch until the 22nm node, and that water immersion lithography would be adequate until then. Recent progress (including shielding the edge of the wafer) had reduced the immersion related defect count to an average of <5 per 300mm wafer, according to Lin.

However, when 32nm half pitch really does become necessary, Lin predicted the industry will have to make some not-so-obvious choices. High-index fluids will not be enough to make production feasible, and multiple exposures with water immersion will have to contend with a depth-of-focus of <140nm, as well as high mask costs. Lin calculated that combating linewidth roughness in EUV lithography will require immense improvements in soft X-ray source efficiency. If there were a maskless e-beam exposure tool with throughput of 15 wafers/hour, that tool would have the lowest CoO of all technologies for wafer runs of up to a few thousand, and for essentially all wafer runs after tool depreciation, he said. Multi-beam writing technology might make such a tool feasible in time, but it would represent a 2x order-of-magnitude throughput improvement over the current state of the art.

Luc van den Hove of IMEC characterized the progress needed to reach 32nm half pitch with three parameters: NA, k1, and λ. Improving NA means finding higher-index materials for the lens, immersion fluid, and resist that also are highly uniform and transparent. Progress is being made, he reported, but too slowly to satisfy IMEC, which needs to be at the leading edge. Reducing wavelength (λ) today means bringing EUV online swiftly with low-roughness resists developed using EUV interference lithography. However, in van den Hove’s opinion, the lowest risk approach was to reduce k1 below the single exposure limit of k1=0.25 (for equal line-space patterns). That can be done using two separate resist films and two exposures. The lowest value he reported was k1=0.14, which would correspond to 21nm CD at λ=193nm and NA=1.3, but with undefined CoO.

In a brief commercial message, Charles Pieczlewski of Sokudo reported that the latest coat development tracks had demonstrated 1nm CD uniformity, more than enough to support ITRS ambitions. A panel of experts from the three major exposure tool companies and Molecular Imprints (representing the next generation) mostly agreed that multiple exposure would keep Moore’s Law alive for the next node, even if the cost of exposures and masks went up. — M.D.L.

Next week, WaferNews will report on tools for immersion lithography and e-beam, new metrology from startup firms, and innovations from companies involving mask substrate tuning and automating OPC.

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