IC integration to system-on-a-chip (SoC) continues to be the dream of all semiconductor companies. Computer and communication companies have driven this trend for decades through finer lithography, better materials, and larger chips and wafers, all leading to higher clock frequency. Cost was not a factor. But the world has changed, and the primary focus today is more functionality at an affordable cost. Even personal computer companies have moved on to dual- and multi-core processors that perform multiple functions on a single chip – spreadsheet on one quarter of the screen, photograph editing on another, watching a movie on the third, and video-conferencing on the fourth. The key challenges to SoC progress, however, are formidable, and include design and design verification, manufacturability, intellectual property (IP) and legal issues, time-to-market, and cost.
To overcome these problems, system companies pursued a different approach to SoC, dating back to the 1980s. Instead of integrating all or most of the system needs on large and complex single chips, they fabricated smaller, high-yielding chips and reconstituted them to behave like large chips as multi-chip modules (MCMs). MCMs saved the computing era back then, even though they were capital-intensive and technology-complex. They still offered a better solution than SoCs by interconnecting dozens of chips in a small, horizontal form factor for high signal speed.
Portable systems such as cell phones brought on a different demand – signal processing, flash memory, and wireless communications in a system that is held in one’s hand and sold at consumer prices. This required a different approach to IC and component packaging, and led the industry to 3-D chip stacking of either bare chips or packaged chips. Since both required interconnections from chip-to-chip, packaging was a critical technology element. This kind of approach was referred to as systems-in-package (SiP). Some view SiP as a vertical MCM, in contrast to horizontal MCMs for high performance computers of the previous era.
SoC, MCM, and SiP are driven by Moore’s Law via the increase in number of transistors per-unit-area. In any given system, such as cell phones, only 10% of the system components are made up of ICs. The remaining 90% are passive components, boards, and interconnections. This so-called 90% of the system problem is being addressed by systems-on-package (SoP), the System Integration Law, measured in functions or components/cm3. SoP addresses this problem by making milliscale discrete components into micro or nanoscale embedded thin-film components, thus reducing system size by 1,000 to million times.
Systems packaging is evolving along with emerging needs of electronic systems. Mainframe computers drove MCMs in 1980s. High-end networking, signal processing, and digital communication demands drive SoC – representing a confluence of previous product classes through integration of technology and design elements from other system driver classes such as microprocessor, application specific IC (ASICS) and analog/mixed signal circuits. Cell phones and handsets are driving SiPs solutions.
SiP helps surpass the limits of the SoC designs. Benefits to SiP include user IP integration, IP reuse, mixed analog/digital design, low design risk, integration of large memories, reduced process complexity, low developmental cost, and shorter time-to-market. In short, SiP brings together ICs including SoCs and discrete components using lateral or vertical integration technologies.
SoP goes a step beyond SiP by integrating thin-film components on a package substrate. By moving global wiring from nanoscale IC (SoC) to microscale on the package (SoP), the latency effect can also be considerably minimized. Wireless components integration limits of SoC and silicon-based SiPs are also handled well in SoP because RF-components such as capacitors, filters, antennas, and high-Q inductors can be better fabricated on a package substrate than on silicon. High-speed, board-level, optical interconnects are moving to the package as chip-to-chip, high-speed interconnections replace copper, addressing both the resistance and cross-talk issues of electronic ICs. In addition, waveguides, gratings, detectors, and couplers can all be embedded in the SoP substrate. The SoP approach becomes even more significant with the emergence of bioelectronics and the need for convergent, micro-miniaturized electronic and bio-electronic systems. The integration of microfluidics, nano-bio-sensing elements, control/feedback electronics, display, and RF/wireless components such as integrated antenna, RFID in a SoP platform makes this technology feasible for future convergent systems.
RAO TUMMALA, Ph.D., professor and director, may be contacted at the Packaging Research Center, Georgia Institute of Technology, 813 First Drive. NW, Atlanta, GA, 30332-0560; 404/894-2652; E-mail: email@example.com.