TSMC rolls out 65nm reference flow

July 17, 2006 – Taiwan Semiconductor Manufacturing Co. (TSMC) has introduced Reference Flow 7.0, offering statistical static timing analyzer, power management techniques, and various DFM enhancements.

TSMC says its design methodology is the first to include statistical timing analysis capabilities, through integration of tools from EDA vendors Cadence Design Systems, Synopsys, and now Magma Design Automation, that analyzes timing effects of manufacturing process variations, to optimize design margins and die yields. Capabilities include statistical SPICE models, library and IP characterization, standard cell design kits, EDA tool enhancements and corresponding design methodologies.

The reference flow also incorporates leakage power reduction technology, including an enhanced voltage island implementation and multi-corner timing closure. A coarse-grained power gating technique helps achieve leakage reductions of up to two orders of magnitude. New power management libraries are also included.

In addition, the flow includes critical area analysis to identify potential random manufacturing defects and drive wire spreading and wire widening corrective actions, as well as virtual chemical mechanical polishing (VCMP) analysis to identify metal and dielectric thickness variation hot spots, and guide dummy metal insertion to improve thickness uniformity throughout the chip. TSMC also has qualified several lithography process check (LPC) post-production tools as DFM compliant.

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