Samsung unwraps 40nm “charge trap flash” device

September 11, 2006 – Samsung Electronics Co. Ltd. says it has created a 32Gb NAND flash device using 40nm process technologies, featuring a “charge trap flash” (CTF) architecture which the company says “sharply” reduces intercell noise levels, and enables higher scalability to enable transition from 40nm to 30nm and even 20nm processes.

In the 32Gbit device with CTF architecture, the control gate is one-fifth the size of that in a typical floating gate structure, and there is no actual floating gate — data is temporarily placed in a “holding chamber” of a nonconductive layer of flash memory, composed of silicon nitride. The CTF design utilizes a TANOS structure incorporating what Samsung calls the first NAND device with a metal layer (tantalum) coupled with a high-k material (aluminum oxide). Samsung first detailed its work with the TANOS structure at the 2003 International Electron Devices Meeting (IEDM).

The 32Gbit NAND flash memory can be used in memory cards with up to 64GB densities.

The new CTF technology “will extend the life span of NAND flash well beyond 40nm level of manufacturing process technology, allowing for greater product miniaturization and greater economies of scale in the production of consumer electronics,” stated Chang Gyu Hwang, president and CEO of Samsung Electronics’ semiconductor business.

Technology features of CTF vs. floating gate

………………………………………..Charge trap flash…………………………..Floating gate

Development……………………2006 (Samsung)……………………….1989 (Toshiba)
Structure……………………Single Gate (Control Gate)…………..Dual Gate (Control/ Floating Gate)
Fabrication
…(cell height)……………..Simple (1/5 of the floating gate)………….Complex
Control gate……………………Height: 1/5 of the floating gate……………–
…………………………………….Material: Metal (TaN)……………………….Polysilicon
Storage level……………..Height: 1/10 of a floating gate……………………–
…………………………………….Material: Nonconduct (SiN)……………….Conduct (poly-Si)
Inter-Cell
…Noise Level………………..No interference………………..Interference at floating gate
Scalability…………………>20nm-level, up to 256Gb…………..>50nm-level, up to 16Gb
Process Steps……………………Reduces process step by 20%………–
Cell Size………………………….Reduces cell size by 28%……………………–

Source: Samsung

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