Avoiding FPGA Packaging Problems BY JOHN RANKIN, AMI Semiconductor Many companies experience extreme problems once their FPGAs get to the package level, not least of which is electrical noise. Most fabless companies cannot afford the time required to troubleshoot and repair the problem because they are already close to, or over, budget for chip designs. The easiest way to avoid FPGA packing problems is to go with a custom ASIC, or switch the FPGA over to an ASIC with a conversion product. The problems associated with FPGA package failures once they are placed on a PCB include time-consuming PCB re-spins, delayed product introductions, and, in some cases, companies being forced to close their doors. The issue has created problems for many PCB designers. Technologically, the main problem is functional failures due to simultaneously switching output noise (SSN). If this happens, a designer’s only recourse may be a total redesign using a different part, such as an ASIC. Lack of documentation, models, and support from FPGA vendors around SI are other issues. SSN grows in severity as interfaces get wider and faster, affecting system performance and decreasing the timing margin by adding to system jitter. In the worst case, if SSN crosses the logic threshold, the system can malfunction altogether. Another symptom of SSN can show up as corrupted memory states. Figure 1. An SI simulation test bench includes chip-level models for high speed I/O, package models on both driver and receiver sides, and system-level connectivity models.Click here to enlarge image SSN is observed as “ground bounce” and can be caused by two different factors: package crosstalk, and noise on the power planes due to high package inductance. To prevent package crosstalk, a good internal device pin-out, including proper distribution of ground/power and signal pins in a package, is critical. Other package crosstalk considerations include reducing the noise of other device-performance pins, such as voltage reference and clocks. It is important to use proper spacing of signals within the package to isolate noise on these pins. Minimizing noise to sustain a clean power supply to the FPGA is critical to maintaining acceptable SI. Noise in the power rail translates to jitter at the output, again decreasing the available timing margins. Optimal signaling requires a good low-inductance package since noise depends on package inductance and the number of simultaneously switching I/Os. Unwanted inductance in the power paths into and out of device packages creates SSN. Failures from SSN are sometimes intermittent, so it is often difficult to trace their cause back to noise in the package. Because of their architecture, FPGAs draw a tremendous amount of power. This higher power consumption causes an IR drop and large switching noise currents. The IR drop exacerbates the noise issue by moving down closer to the thresholds and slows down the gates, hurting timing margins. The focus of the FPGA supplier has been on squeezing the most functionality into a single package for the lowest cost. Packages housing FPGA devices are designed to meet the needs of the widest possible number of applications, and compromises are often made to produce the lowest possible price. As a result, packaging problems – SSN, package noise, and signal integrity issues – occur more often when using an FPGA than an ASIC, which is custom-designed for a single application. Therefore, many FPGA conversions are implemented due to the need to overcome these noise issues. In many instances, FPGA suppliers use third parties for both package design and supply who offer design services to both IC and PCB designers. While FPGA suppliers are becoming aware of the problem, they note that the entire system, including PCB and FPGA, needs to be optimized for SI, and also that they have no control over customer-designed PCBs. ASIC suppliers work closely with the customer’s system and PCB designers to optimize signal integrity. For example, one company* designs packages using both 2- and 3-D modeling and checks inductance and SI with test circuits. They provide input/output buffer information specification (IBIS) models to customers and, on demand, will provide 3-D models. Another company** provides IBIS models and will license their scatter-parameter (S-parameter) and simulation program with integrated circuit emphasis (SPICE) models. While the package models help, they don’t incorporate coupling to other signals on the package. Additionally, there is no standard package model format, and 3-D models are complex. There are some design practices that an FPGA designer can use to minimize SSN, such as not bunching output drivers together on the layout, slowing down the edges for devices that have programmable slew-rate drivers, and staggering device timing to minimize the simultaneous switching on the buses. It may take some, or all, of these options to get the system to work, and many are not available on all FPGAs. ASIC packages, on the other hand, can be custom-designed with particular attention paid to matched-pair traces through the substrates, noise-reducing ground planes, and special routing specific to certain design requirements. Even in packages that are designed to be pin-for-pin compatible with the FPGA package offerings, special attention can be paid to noise issues. A related issue to SSN package problems is how the package design affects a design’s SI. In the past, SI has been a concern usually associated with multi-gigabit serial interface design. Today, it is an aspect of design that engineers building high-speed parallel interfaces can no longer ignore. As speeds increase, bit periods shrink, reducing the available timing margins. High-speed interfaces can run at greater than 500 Mbps/per line, with rise times in the hundreds of picoseconds. Any noise on the transmission lines eats into the available timing margins. With structured ASICs***, SI is addressed in the structured ASIC architecture, and has become the responsibility of the ASIC vendor when a designer uses the vendor’s design methodology. Since clocks, I/Os, and power grids are part of the fixed layers of the structured ASIC fabric, the clock skew characteristics are pre-characterized and SI issues, such as IR drop, can be accounted for during physical synthesis. The vendor is entirely responsible for clock skew, DFT, and signal integrity issues. Whether designing for FPGAs, structured ASICs, or cell-based ASICs, simulating for SI issues must be part of the overall design flow. The goal of an SI flow is to ensure high-speed I/O designs meet their specifications in real applications. Ideally, simulation is done before silicon is built, allowing multiple quick and easy design iterations if problems are found, a much better – and less costly and time consuming – flow than debugging silicon. Therefore, accurate simulations are critical in the design process. Accurate simulations require accurate modeling. An SI simulation test bench (Figure 1) includes chip-level models for high speed I/O, package models on both driver and receiver sides, and system-level connectivity models for PCB trace, vias, etc. SI analysis on high-speed I/O requires precise modeling of each package trace, from the die pad to the bond wire, and from the substrate trace to the solder ball (assuming a BGA package). The typical practice is to provide a lumped model characterized by R, L, and C for the package trace of interest. The lumped model is adequate as long as the circuit element size is smaller than the wavelength of the operating frequency – usually less than 200 MHz. But the package-lumped model loses accuracy as the signal frequency increases above a few hundred MHz. Modeling package effects with S-parameters is more accurate than the lumped modeling approach for frequencies over several hundred MHz. The S-parameter modeling approach was found to provide results that correlated well with lab measurement. A signal integrity flow that creates the S-parameters and integrates the S-parameter matrix into the simulation bench for their high-speed applications is now being used. Conclusion The days of ignoring the design and layout of the package and its effect on device performance and functionality are over. FPGA and ASIC designers must include accurate SI modeling in their designs especially as device frequencies approach the multi-hundred mega-Hertz range. While FPGA packages can be the best price, they are not always the best solution for high-speed applications. Cell-based and structured ASICs offer the ability to create custom low-noise packages for specific designs. One solution for converting an FPGA design and also increasing its performance is with a pin-for-pin-compatible, lower-noise package. S-parameters extracted from full-wave, 3-D simulations offer the accuracy needed to insure correct ASIC operation in the system application, and can be used as part of an ASIC design flow to insure that there are no SSN or SI surprises when silicon is put onto the PCB. * Altera ** Xilinx *** XPress Array II JOHN RANKIN, senior product marketing engineer, may be contacted at AMI Semiconductor, AMI Semiconductor 2300 Buckskin Rd. Pocatello, ID 83201; 208/233.4690; E-mail: email@example.com.