BY ELS PARTON, and WIM CHRISTIAENS, University of Ghent
Bendable chips are a key component of future smart systems such as smart textile and flexible displays. Such ultra-thin chips can be embedded into PCBs, enabling system miniaturization. Engineers at IMEC and Ghent University in Belgium developed a new process flow realizing ultra-thin chip packages by packaging ultra-thin chips of only 20 to 30 µm between 2 polyimide layers, resulting in a 50-µm-thick bendable packaged die.
Figure 1. Process steps for the new packaging technique for ultra-thin chips.
Presently, 3-D chip stacking enables system miniaturization by embedding bare die in the inner layers of the PCB and connecting the chip pads to print wiring. An alternative approach is to provide an interposer substrate for the die before embedding. This offers the advantage of testing the chip before embedding – addressing the known good die problem. Furthermore, a contact fan-out with more relaxed pitches can be provided, which eliminates the need for precise placement and ultra-high-density PCBs. However, this approach can only be used if the die and interposer layers can be made ultra thin.
The process flow for packaging ultra-thin chips starts with a 20-µm polyimide layer base substrate that is spin-coated on a rigid glass carrier, which is removed at the end of the process. Silicon chips, thinned down to 20-30 µm with 100-µm contact pitch, are placed onto this polyimide substrate. Benzocyclobutene (BCB) is used as adhesive because it offers high bond strength and can resist the top polyimide layer’s high curing temperature. Another advantage to using BCB as an adhesive is that it allows for void-free bonding. After the chip is fixed to the polyimide layer, a second polyimide layer (20 µm) is spin-coated to cover the chip. To ensure good adhesion between top and bottom polyimide layer, the cured bottom layer is first plasma-treated – CHF3/O2 and subsequent O2 plasma treatment – then contact openings to the bumps of the chips are realized through the top polyimide layer. Small microvias with top diameter down to 35 µm are created using laser drilling with a tripled yttrium aluminum garnet (YAG) laser with a shaped beam. Finally, a top metal layer (1 µm TiW/Cu) is sputtered, metallizing the contacts to the chip and providing a fan-out. The result is a 50-µm-thick chip package.
Figure 2. Flexible chip.
This ultra-thin package can be embedded in a stack of PCB layers or can be used as flexible chip in smart textile (Figure 2). The process flow also provides an alternative for the driver chips in certain types of flexible displays. In such displays, a base polyimide layer is applied on a rigid substrate, followed by processing of an active matrix of thin-film transistors (TFTs). Each TFT cell addresses one pixel in the display. The rows and columns of the display are driven by external silicon chips, which are packaged in tape-carrier-package or chip-on-film format and attached to the display substrate using adhesives or solders. Alternatively, the ultra-thin package technology can be used for embedding the driver chips in the polyimide base substrate, before processing the active matrix. This results in enhanced flexibility for the display module and a strongly reduced number of interconnections from the display substrate to the external driver electronics.
The new concept of packaging ultra-thin chips results in a flexible packaged die of only 50 to 60 µm. Vias with diameters down to 35 µm are created using a tripled YAG laser, enabling chips with contact pitches down to 60 µm. The new process flow provides an interposer, permitting testing of the chip before embedding and providing a contact fan-out with more relaxed pitches.
ELS PARTON, Ph.D., scientific editor, may be contacted at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; +32/16 281467; E-mail: Els.Parton@imec.be. WIM CHRISTIAENS, electrical engineer, may be contacted at TFCG Microsystems, Technologiepark 914A, B-9052 Gent; +32/9 264 53 71; E-mail: Wim.Christiaens@elis.ugent.be.