High-k Technology Shrinks Transistor Size

(January 29, 2007) YORKTOWN HEIGHTS, NY &#151 IBM announced it is in the development stage with 45-nm transistor technology that uses high-k gate dielectric and a proprietary metal composite for the transistor gate electrode. Constructing the transistor with conventional methods such as high-temperature annealing &#151 instead of removing and recreating the gate post-build &#151 is a familiar process that gives engineers more control and reduces the possibility of error, said Ghavam Shahidi, director of silicon technology at IBM.

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>

LIVE NEWS FEED

NEW PRODUCTS

Compact point of use fluid delivery heater replaces multiple components in a system
07/22/2015Watlow, a designer and manufacturer of complete thermal systems, announces its new point-of-use fluid delivery heater...
New fiber optic temperature sensing and control system ideal for RF environments
07/22/2015Watlow, a designer and manufacturer of complete thermal systems, announced its new EZ-ZONE RM fiber optic temperature me...