High-k Technology Shrinks Transistor Size

(January 29, 2007) YORKTOWN HEIGHTS, NY &#151 IBM announced it is in the development stage with 45-nm transistor technology that uses high-k gate dielectric and a proprietary metal composite for the transistor gate electrode. Constructing the transistor with conventional methods such as high-temperature annealing &#151 instead of removing and recreating the gate post-build &#151 is a familiar process that gives engineers more control and reduces the possibility of error, said Ghavam Shahidi, director of silicon technology at IBM.

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>

NEW PRODUCTS

SEMI-GAS Xturion Blixer enables on-site blending of forming gas mixtures
10/03/2017The Blixer provides a cost-effective alternative to purchasing expensive pre-mixed gas cylinders by enabling operators to blend ...
Automated thickness measurement system speeds production
09/20/2017ACU-THIK is an automated thickness measurement tool incorporating dual contact probes for high accuracy inspection of semiconductor wafers....
3D-Micromac launches the second generation of its high-performance microcell OTF laser systems
04/17/2017The high-performance production solution for Laser Contact Opening (LCO) of PERC solar cells achieves a th...