High-k Technology Shrinks Transistor Size

(January 29, 2007) YORKTOWN HEIGHTS, NY — IBM announced it is in the development stage with 45-nm transistor technology that uses high-k gate dielectric and a proprietary metal composite for the transistor gate electrode. Constructing the transistor with conventional methods such as high-temperature annealing — instead of removing and recreating the gate post-build — is a familiar process that gives engineers more control and reduces the possibility of error, said Ghavam Shahidi, director of silicon technology at IBM.

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>

NEW PRODUCTS

Dynaloy unveils safer cleaners
11/19/2014In response to evolving industry trends and customer preferences for products with better environmental, health, and safety (EHS) profiles, Dynaloy LLC is launching three...
Entegris' VaporSorb filter line protects advanced yield production
10/21/2014Entegris, Inc. today announced a new product for its VaporSorb line of airborne molecular contamination (AMC) filters. ...
Next-generation nanoimprint lithography technology
10/21/2014EV Group (EVG) today introduced its SmartNIL large-area nanoimprint lithography (NIL) process....