High-k Technology Shrinks Transistor Size

(January 29, 2007) YORKTOWN HEIGHTS, NY — IBM announced it is in the development stage with 45-nm transistor technology that uses high-k gate dielectric and a proprietary metal composite for the transistor gate electrode. Constructing the transistor with conventional methods such as high-temperature annealing — instead of removing and recreating the gate post-build — is a familiar process that gives engineers more control and reduces the possibility of error, said Ghavam Shahidi, director of silicon technology at IBM.

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>

NEW PRODUCTS

Entegris announces GateKeeper GPS platform
07/15/2014Entegris, Inc., announced last week the launch of GateKeeper GPS, its next-generation of automated regeneration gas purification system (GPS) technology....
Bruker introduces Inspire nanoscale chemical mapping system
07/15/2014Bruker today announced the release of Inspire, the first integrated scanning probe microscopy (SPM) infrared system for 10-nanometer spatial...
MEMS wafer inspection system from Sonoscan
06/25/2014Sonoscan has announced its AW322 200 fully automated system for ultrasonic inspection of MEMS wafers....