Litho, materials, manufacturing efficiency top SEMATECH meeting agendas

January 29, 2007 – Extreme ultraviolet lithography (EUV) and 193nm immersion lithography will be a primary focus of SEMATECH’s 2007 Knowledge Series seminars in the upcoming year, the group said today in a statement. Other areas will include materials to enhance transistor and backend development, and methods to improve manufacturing efficiency and yield.

Two workshops over the next several weeks in San Jose, CA, will address EUV mask standards — one seeking to review and improve EUV mask carrier/handling and load port standard requirements needed for the SEMI specification document, and another to define and reach agreement on specifications for fiducially mark/ID pattern attributes for EUV mask blanks. Other workshops and symposiums held in late October-early November in Japan target various EUV challenges and technology/performance updates relating to sources, masks, optics, resists, contamination control, and metrology. Immersion lithography, meanwhile, is the focus of the 4th International Symposium on Immersion Lithography (Oct. 8-11, Keystone, CO) — produced in cooperation with IMEC and Selete — to discuss progress in high-index 193i lithography, and build consensus on emerging critical issues

For materials scientists, SEMATECH has events about once a quarter in 2007. A surface preparation and cleaning conference (April 24-26, Austin, TX) will encompass wafer frontend, wafer backend, advanced mask, and environmental, safety, and health issues in semiconductor cleaning. The International Symposium on Advanced Gate Stack Technology (Sept. 26-28, Dallas, TX) will host discussion about current technical challenges for high-k/metal gate stack implementation for the 45nm technology generation. And an alternate channel materials workshop (Dec. 2007, Washington, DC) will focus on R&D directions on new channel materials and new device structures for future MOSFET technology.

Various manufacturing meetings during the year (Apr. 18-20/Dresden, Sept. 15-19/Indian Wells CA, Nov.29-30/Tokyo), sponsored by ISMI, address advanced process control. ISMI’s technical seminar in Japan (date TBD) will review regional program activities and papers, and update IC manufacturer requirements and standardization activities. ISMI’s Symposium on Manufacturing Effectiveness (Oct. 22-25, Austin, TX) will again focus on reducing manufacturing costs and increasing productivity across a range of areas, including equipment and fab productivity, fab design, statistical methods, e-manufacturing, design for ESH, and yield/metrology.

Finally, a series of seasonal meetings (Apr. 25/France, July 18/San Francisco, Dec. 5/Tokyo) will address updates and revisions to the International Technology Roadmap for Semiconductors (ITRS), with participants providing input to the Roadmap’s technology working group teams.

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