Methodology and Flow Challenges in Multi-die Package Design

Technology shifts in consumer electronics present manufacturers with a laundry list of challenges. The numbers of required transistors to allow for new features and functionality – coupled with shrinking die sizes and higher clock speeds needed for improved levels of performance – is driving IC designers to use smaller process nodes. Additionally, IO counts are skyrocketing as more functionality is built into the die.

These challenges have driven the demand for system designs that require increased, and more individually complex, design constraints. More than 80% of signal interconnect must be carefully designed into the packages and boards that make up today’s sophisticated consumer electronics. Existing package design solutions have significant limitations, because they’re designed to use die that have a fixed interface, resulting in a siloed and one-way design process with manual collaboration as the only way to optimize across domains.

In the traditional serial approach shown in Figure 1, each library component acts as a gate in the process. Detailed package design is delayed until the IC footprint is available, subsequently delaying PCB design. This serial approach limits any significant reductions in design cycle. Once the package has been incorporated into the board, routing issues may force changes to the final ball out of the package and may cause significant delays in the overall system design cycle.

Figure 1. System design environment.
Click here to enlarge image

Designers need a collaborative engineering approach where constraints are optimized across different implementation fabrics. This new approach requires converting the serial process to one in which each of the design disciplines can run concurrently; enabling design optimization across all three disciplines; and efficiently managing the complex connectivity, constraints, and interfaces among IC, package, and PCB.

Concurrent Co-design Across Design Disciplines

The obvious path to design cycle reduction lies in creating an efficient concurrent co-design flow. Each environment has different flows and is driven by different users that are typically working in different locations. Each individual flow executes asynchronously, so to support a concurrent process they must be able to synchronize changes made concurrently or establish data owners to facilitate smooth synchronization processes. The new flow allows each discipline to propose interface changes. The disciplines have the ability to accept or reject these changes, and merge with changes made in the local environment. Finally, each discipline can validate its interfaces with the other in real time using a synchronization engine. The key to the concurrent co-design requirement lies in the ability to manage the connectivity of each fabric independently while allowing for concurrent changes that can be easily synchronized between disciplines.

Managing Complex Connectivity and Constraints

Connectivity for a single-die package has never been a tough problem to solve. In most cases, the only reason to use a logical netlist tool was to easily assign an IC bump to a specific package ball. Some designers leveraged standard schematic tools for this process, thus providing a commercial solution for generation of the netlist and management of constraints. As IC and package pin-counts grow, this approach becomes tedious and error prone. Each high-pin-count device must be split across numerous graphical symbols, which transforms the schematic into a large connect-by-name drawing instead of a meaningful graphical representation.

Custom solutions designed to leverage standard productivity applications required the user to capture connectivity by encoding signal name to pin number connections into a spreadsheet. This solution was appealing to engineers because they were already familiar with the application from calculating timing budgets and defining constraint sets. The flexibility of spreadsheets lends itself to complex designs, especially in a multi-die package, such as a system-in-package (SiP).

Overriding these benefits are a few significant limitations. Custom software is required to generate a netlist that can drive a package layout tool, adding development and maintenance costs. Changes to connectivity made in layout are not easily updated in the spreadsheet. Synchronization between the spreadsheet and layout must be developed. No connectivity engine is available for defining constraints that require pin-pair objects. Additionally, there is no efficient way to add, delete, or modify IC and package definitions from the design, which means updates to the IC and package interfaces must be made manually. Given the complexity of this task, errors become commonplace.

Figure 2. The role of the connectivity management system in the solution.
Click here to enlarge image

What is really needed is a mixture of these two historic approaches that is flexible enough to address the concurrent requirements of all three design environments. The optimal connectivity management solution allows an engineer to define connectivity in a spreadsheet format; define basic and advanced constraints including pin-pair constraints that require a dynamic connectivity engine; import die and package abstracts quickly from various CSV and HDL formats; perform ECOs on die and package abstracts and auto-update the connectivity; generate physical netlists to drive package layout; synchronize the logical and physical design and get immediate visual differences of the two databases; and integrate seamlessly with the PCB environment thus providing arbitration between changes made in the IC, package, and PCB fabrics.

Concurrent Co-design Flow

Success in a complex concurrent co-design process requires adherence to a flow and careful review of the synchronization results along the way. Figure 3 demonstrates the flow and highlights the points where synchronization is critical.

To start the design flow, Verilog from the IC design is provided to the engineer responsible for managing package connectivity. The Verilog is then imported to build an abstract model of the interface. This defines the object to be co-designed between the package and IC environments. Fixed die, bypass, and termination components are added to the design and connectivity is defined in the spreadsheet interface.

Figure 3. Steps in IC/Package/PCB co-design process.
Click here to enlarge image

A physical netlist is generated and used to define the initial database. The physical die co-design process is initiated and IO planning environment is seeded with Verilog from the logical design. The IO ring is placed, a bump matrix is defined, and nets from the Verilog are assigned to the bumps. A package interface is defined in layout; package signals can be auto-assigned to the balls. All IO assignments and connectivity changes made in the package layout are updated in the connectivity management solution using the synchronization engine.

The package-PCB interface is transferred to the PCB environment – thereby auto-creating a component that can be used in the logical PCB design environment. PCB connectivity is captured using the newly created component. The physical PCB design environment is updated with a new netlist allowing for optimization of the package/PCB interface within the context of the board. Any changes required to optimize the physical package-board interface are updated in the logical PCB environment using the synchronization engine. The package design is then updated with the optimized interface as the SiP design imports the updates from the logical PCB design environment. This updates the existing package interface, retaining internal connectivity. A physical netlist is generated and used to update the physical package database. The layout designer must decide whether to address the interface changes in package routing, or push the change into the IC design. The final step is to update the IC design in the case where some of the IO changes are to be implemented in the IO assignment.

Once these steps have been completed, the IC, package, and PCB environments are in concurrent co-design mode. Synchronization occurs by following these standard interface steps. This iterative process allows input from each of the three design environments to ripple through the system and eventually update the other designs. ECOs can be triggered from any of the points in the process. A common ECO would be the import of a new Verilog into the logical SiP design. This would trigger the steps in the IC/Package/PCB co-design process that would result in the synchronization of the databases in all three domains.


Old serial processes, minimal integration between design fabrics, and lack of a common connectivity solution limit the efficiency of design teams. Today’s designs require new, robust design flows with co-design capabilities that bridge the communication gap between IC, package, and PCB environments. The only way to efficiently optimize across these solutions is by managing design tradeoffs that are constantly being made in the IC, package, and PCB.

STEVE DURRILL, architect, and KEITH FELTON, product marketing group director, may be contacted at Cadence Design Systems; E-mail:;


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>



Astronics Test Systems announces new PXIe test instruments
01/24/2017Astronics Corporation, through its wholly-owned subsidiary Astronics Test Systems, introduced two new test instruments today. ...
Edwards launches new Smart Thermal Management System at SEMICON Europa 2016
10/25/2016Smart TMS helps semiconductor, flat panel display and solar manufacturers improve their process performance and safety by red...
Tektronix introduces Keithley S540 power semiconductor test system
10/19/2016Tektronix, Inc., a worldwide provider of measurement solutions, today introduced the Keithley S540 Power Semiconductor Test System, a ...