Vistec, Japan’s TOOL combine tools for faster layout recipes

April 13, 2007 – Vistec Semiconductor Systems GmbH and TOOL Corp. say they have integrated Vistec’s LWM9000 SEM-based CD measurement system with TOOL’s Lavis layout visualization platform, making it possible to display measuring layout design data and visually create recipes.

More complex process nodes require reliance upon and more diversity in resolution-enhancement techniques, and high-precision measurement technology to measure pattern defects is needed in addition to optical proximity correction (OPC) and other defect-inspection techniques to improve chip yield rates, the companies claim, in a statement. Recipes that include information such as coordinates and criteria of measurement regions must be highly accurate — so reduction in time required to create these recipes improves the efficiency of the mask making process.

“The integration of highly accurate CD measurement system LWM9000 SEM and multi-functional layout platform Lavis provides our mutual customers with dramatic improvement in their measurement processes,” said Hideaki Hontao, president of TOOL, in a statement.

“Collaboration with TOOL succeeded in every way,” added Gerhard Ruppik, GM of Vistec Semiconductor Systems.

Earlier this year TOOL inked a deal with Brion to integrate its Lavis system with Brion’s Tachyon OPC and RET/OPC verification system, combining Lavis’ large-volume data handling and high-speed data display capabilities with Tachyon’s ability to execute high-speed, full-chip simulation and inspection with high precision. The companies claim that user feedback suggests a 90% reduction in time required to create a recipe vs. creating it manually.


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