May 14, 2007 – STATS ChipPAC has formally established its new R&D facility in Singapore, to develop next-generation technologies including through-silicon vias (TSV), microbump bonding methods for 3D die, silicon substrate-based system-in-package solutions, and embedded active die technology.
The new facility includes >10,000 sq. ft. of cleanroom space (Class 10-10,000), which can be nearly doubled for future expansion needs. The R&D operation will “specialize in wafer-level processing,” with an equipment set for photolithography, plasma etching and deep reactive ion etching (DRIE), wafer thinning, and wafer bonding, the company said in a statement.
Operations at the new Singapore R&D site will seek to expand on the company’s silicon-based offerings including integrated passive networks such as baluns, filters, and amplifiers, for new integrated passive devices, in addition to work on TSV, 3D microbumps, etc.
“The new facility fulfills an important role in the Company’s global R&D strategy and will augment our current worldwide R&D operations focusing on advanced packaging solutions,” stated company CTO Han Byung Joon.