IMEC discloses finFET progress, but 32nm introduction still hazy

June 13, 2007 – Providing updates on work performed with its 32nm CMOS research partners at this week’s VLSI Symposium, IMEC says it has improved its process to yield “reproducible” finFETs with fin widths down to 5nm, and high aspect ratios, using 193nm immersion lithography and dry etching. Use of ultrathin body devices eliminates the need for channel doping, resulting in reduced parametric spread due to dopant fluctuations together with reduced junction leakage.

The consortium disclosed its work using a ring oscillator with metal gates and undoped fins, which achieved an inverter delay of 13.9 picoseconds at a 1.0V supply voltage and 1.9nA off-current — the best low-power performance of finFETs ever reported from undoped channels and improved subthreshold characteristics, IMEC stated. “SRAM cells and data path demonstrators with low standby current and good low operating power performance were realized,” according to the group.

IMEC also said it has devised a way to improve both negative- and positive-bias temperature instability of the finFETs, by dielectric passivation involving introduction of fluorine into the metal/Hf-based gate stack during gate etching. The “novel, effective, and cost-efficient method” requires no extra processing step, IMEC noted.

The 13.9ps switching time is the same as that reported by Infineon, also at this week’s VLSI Symposium. Despite positive results (both in this work and earlier results shared at last December’s IEDM conference), both Infineon and IMEC contend that finFETs likely will not be used in mass production until at least the 32nm node. “Although the performance benefits of FinFETs have been recognized for many years, several bottlenecks have to be overcome to bring finFET technology to manufacturing. These advances have reduced the gap for finFETs to become a manufacturing technology,” said Luc Van den hove, COO IMEC, in a statement.

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