by Debra Vogler, Senior Technical Editor, Solid State Technology
In what it claims is validation for imprint lithography for 22nm CMOS, Molecular Imprints Inc. (MII) is touting results from Toshiba, reported at the 33rd International Conference on Micro-and Nano-Engineering (MNE, Copenhagen, Denmark, Sept. 23-26), which show defect levels “very similar” to those seen in the early days of immersion lithography’s introduction.
Using step-and-flash imprint lithography (S-FIL), Toshiba says it was able to achieve isolated 18nm features with <1nm critical dimension uniformity (CDU), and <2nm line-edge roughness (LER), and the defect density from all sources on a full-field imprinting tool (depending on the measurement system's sensitivity) ranged from a little over 5 to ~0.3/sq cm. "These are defect levels that were very similar to where immersion lithography was at the same stage of its introduction into use," said Mark Melliar-Smith, MII's CEO, in a briefing with WaferNEWS. Toshiba also achieved results for 24nm dense lines and spaces, structures used to investigate advanced memory structures.
The overlay (OL) reported was 20nm, 3σ, mix-and-match (i.e., not single tool), which represents “very rapid improvement,” noted Melliar-Smith. “We’re looking to driving the OL down to whatever the industry will need [...] a couple of MII’s end users view OL as the ‘long pole in the tent.’”
The data was obtained on MII’s Imprio 250 system, which was delivered to Toshiba in January, installed by the end of March, and accepted in <10 weeks, according to Melliar-Smith. "In my mind, that's a very commendable schedule for a first tool in a pretty complicated technology such as they are fabricating," he said, adding that moreover, "it demonstrates to the world the ease of use of the core imprint technology." He further noted that MII delivered a complete system (tool, sources, materials, process) and the company has received infrastructure support from the rest of industry, citing the fact that all the imprint masks were provided by DNP.
Readiness for the 22nm design node, when some do not expect EUV to be ready, is a key issue. “We’re in this business because we believe we have the best NGL solution bar none, and our intention is to have high-volume manufacturing tool capability with all the requirements (i.e., defects, resolution, throughput, CoO, infrastructure, etc.) available for when the industry needs it,” said Melliar-Smith. He thinks the 22nm design node is a good estimate for when NGL will be required, and he told WaferNEWS that the likely choice will be imprint lithography, noting that several of the challenges facing EUV are much higher-risk than those facing imprint lithography.
This latest news about Toshiba’s work at 22nm follows an earlier announcement that MII received a fourth order for its whole disk imprinter tool (for HDDs) (Imprio 1100), representing a third different end user for the system. This technology is geared for dimensions of 20nm and below, which are typically isolated squares, i.e., contact “windows.” “We see this as a very big market,” said Melliar-Smith, noting that developing and selling tools into this industry is synergistic with CMOS — “The tools are the same, the templates are made with the same sort of technology, the processes are very similar.” The difference between the two applications is that one uses a whole wafer tool and the other a step-and-repeat tool. – D.V.