Moore’s Law to head z-ward?

by Bob Haavind, Editorial Director, Solid State Technology

With the trend toward 3D integrated circuits gaining momentum, SEMATECH organized a workshop in Albany, NY earlier this month (Oct. 11-12) as it plans to move its work on 3D from Austin to its New York branch. Why does every chipmaker have 3D approaches using through-silicon vias (TSVs) on its roadmap as the industry heads toward 32nm and beyond? There are four main drivers, explained Phil Garrou, Microelectronic Consultants of North Carolina, in an opening overview of the field:

– Failure of low-k dielectric integration, due to persistent problems with mechanical failure, delamination, etc.;
– Latency and processing speed for multi-core processing, which could be aided by shorter traces (TSVs) in the z-axis within bonded chip stacks;
– Hetero-integration, or stacking a variety of chips requiring different processes; and
– Form factor — such as stacking up to eight memory chips in a package taking the same space as a single chip.

As 3D has progressed, it has become clear that electrical performance can be superior to that of system-on-a-chip (SoC) approaches, with the added advantage of being to optimize processes for each chip in a stack.

Garrou also cited a recent report by IBM, Toshiba, and Samsung that found no difference in electrical performance between 32nm and 22nm chips. If there is no performance advantage, he noted, why go to the huge expense of changing lithography and processes for 22nm when a similar form factor could be achieved by stacking chips using 32nm features?

While extensive development of 3D methods will be needed to achieve true hetero-integration, which may be a number of years off, the techniques are already being employed with memory chips. In fact, according to Garrou, a face-to-face bonded processor and memory stack was designed into Sony’s PlayStation 3, enabling the use of 90nm chips rather than having to go to 65nm. Seven Japanese companies are now working on 3D image processing chips (for cameras), he added, with one full side for imaging and TSVs to the backside to connect to processing circuits.

“The easy stuff will be first,” Garrou suggested, especially flash memory and other memory stacks, followed by image processing stacks.

The TSVs generally are etched deep into a wafer or chip, similar to trench capacitors for memory chips, and then the backside is thinned away up to the bottom of the vias. Copper “nails” can be deposited to make contact between wafers or chips that are bonded into stacks. Die are repartitioned to achieve closer trace distances from block to block than could be done on an SoC.

Because of these shorter signal paths, some cite the potential for 35%-40% reductions in interconnect lengths in the 3D approach vs. a conventional horizontal surface layout. But a number of speakers at the workshop pointed out that chip architects already had optimized most layouts to eliminate long traces, so that 5%-10% reductions seem more likely. A potential advantage discussed during the Q&A session would be to cut down on interconnect layers on a chip — for example, putting a processor and DRAM on separate chips and connecting them with TSVs might reduce interconnect layers from eight to five, and thus reduce processing costs.

Myriad problems remain, however, before 3D can be effective beyond simple memory stacks. Thermal design will be one of the toughest, and so that was the focus of the SEMATECH workshop. Hot spots within a multichip stack will make heat removal challenging, and thinning either wafers or chips will make the problem even worse, speakers pointed out. Numerous approaches to dealing with thermal problems were discussed, although work enabling physical modeling of heat flow through a stack is just being initiated, so it is not yet clear how well most of them would work.

While thermal metallized interposers between chips might help remove heat, they also would lengthen signal paths, so some speakers felt they were an unlikely solution. A technique mentioned by a number of presenters was to simply add extra vias in hot spot areas, to conduct away heat. Jason Cong, et. al., UCLA, discussed work going on to extend EDA to deal with thermal analysis and to determine the number of extra vias needed to reach a target temperature. If the analysis is not optimized, it might lead to using 2.5x more vias than needed to reach the target, he said.

But Muhannad Bakir, research engineer at Georgia Tech, suggested that very large numbers of vias would be needed for heat removal in gigascale systems, and an air-cooled heat sink at one end of the stack would have to be much larger than the die to be effective. As an alternative, Georgia Tech is investigating microfluid channels with multi-layers of cooling within a chip stack. Since the researchers are also exploring optical signals, they have developed what they call “trimodal planar interconnects” using hollow polymer pins and fiber optics.

A single-phase, microfluidic cooling system with about 2W pump power at some 2.1 atm pressure could remove 800 W/cm2 from a chip stack, according to Bakir. He said that the researchers had learned that work on microfluid cooling was going on elsewhere, as well as at Georgia Tech.

Another approach might be thermoelectric cooling, discussed by Seri Lee of Nextreme, using copper pillar bumps. P and n elements about 10-20μm thick might form a heat pump to remove heat, although extra vias to conduct the heat would still be needed according to Lee.

Some have suggested that 3D designs should be based on 3D placement and routing and sophisticated standard cell placement algorithms. This is wrong, according to Ruchir Puri, IBM T.J. Watson Research Center. 3D needs to be exploited at the architectural level, including physical planning. Wire length is not the most important criteria, he said, timing and critical paths are what needs to drive co-design of chip performance and power, including thermal design and a physical view. 3D architecture and performance must be linked to thermal analysis.

“We need thermally aware design tools,” Puri said.

To achieve yield, it would be desirable to assemble thinned chip stacks of known good die. But since bonding and connecting operations may create new faults, testing would have to be duplicated after assembly, doubling test costs, some speakers pointed out. Instead, less complete testing might be done, so that “pretty good die” are assembled to keep costs down. Once a 3D stack is assembled, access to circuits within the stack will be limited, so built-in self-test structures and sophisticated testing strategies will be needed.

As the industry moves down to 32nm and beyond, physics constraints will force so many changes in materials, processes, and device structures, that even if solutions can be found, they may be very expensive and time-consuming to develop and put into production in fabs. This appears particularly true for lithography. As a result, suggested Robert Patti, founder and CTO of Tezzaron Semiconductor, Naperville, IL, we may see much more subtle shifts down the node scale well beyond the half-node shifts of past cycles.

While the industry struggles to continue on the Moore’s Law track, doubling the number of devices per chip area every two years, 3D approaches, first using bonded chip or wafer stacks with TSVs, and then building multi-layers of circuitry right onto the chip, may provide an interim solution if the shrink slows down. — B.H.


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