Toshiba, SanDisk ramping 43nm NAND flash with HK+MG, 3b/cell

by Paula Doe, Contributing Editor, Solid State Technology

Toshiba Corp. and SanDisk Corp. aim to increase their share of the NAND flash market by bringing down costs, as they accelerate the ramp of their new Yokkaichi Fab 4 next year, introducing 43nm geometries, high-k/metal gates, second generation 1.3NA immersion lithography, and 3 bits per cell. Executives from both companies detailed their current production plans and future roadmap for flash memory technology to Solid State Technology partner Nikkei Microdevices in Tokyo.

Toshiba aggressively projects demand for NAND flash storage capacity to more than double every year through 2010, for a 30X total increase over 2006 (see Fig. 1), dependent in part on falling price/bit. So the companies now plan to ramp Fab 4 to 80,000 wafers/month in 2008 and 210,000 in 2009, a 40% increase over the original plan. “We initially planned Fab 4 for 150,000 wafers/month, for which we and Toshiba planned to invest a combined $5.5 billion (¥600B),” SanDisk chairman and CEO Eli Harari told Nikkei Microdevices. “Now that planned capacity has been increased to 210,000, investment will be higher.”

Toshiba will put some 70% of its $6.5B/¥715B capital investment budget for 2008-2009 into NAND flash, primarily toward the additional capacity at Fab 4. With that fab now slated to reach full capacity by 2009, the company says it will decide on adding an additional flash fab by this spring. Toshiba officials say they could fill only 75% of orders this fall. Harari says SanDisk’s wide range of customers makes its demand more stable than at some competitors.

Volume production was to start in December at 56nm at Fab 4, with first phase installed capacity of 42,000 wafers/month. In early 2008, production will start to switch over to 43nm, which will be the fab’s primary output. The partners introduced immersion lithography for 56nm in Fab 3 in early 2007, and ramped that to 90% capacity within the year.

“We struggled over the ramp of immersion,” Yokkaichi fab GM Noriyoshi Tozawa told Nikkei Microdevices. “But now that it’s in use in standard production, the switchover to 43nm should go smoothly.” He notes that for 43nm the fab has added new 1.3NA immersion scanners and new deposition tools for high-k/metal gates. A hafnium oxide is used for the inter-poly dielectric separating the control gate and the floating gate, and a metal silicide replaces polysilicon in the control gate. The improved materials allow the floating gate to be made flatter, reducing the cross talk between cells for more reliable data writing and reading (see Fig. 2).

The companies count on adding another level of multilevel cell technology to significantly bring down costs by increasing the data storage capacity of each chip. Toshiba reports that almost 100% of its 56nm production is now 2 bits/cell, and development of technology for 3 bits/cell is almost completed. It plans to start shipping samples before the end of 1Q08, and expects to start commercial production in the second half of next year.


(Source: Toshiba, Nikkei Microdevices)

Storing 3 bits/cell requires distinguishing eight different voltage levels, but adds 50% more storage capacity per chip for essentially the same cost. It could also mean Fab 4 output in bit count in 2008 could be up 5X-8X from 2007. Toshiba/SanDisk is apparently the only memory supplier to date to announce a target shipping date for 3 bits/cell NAND flash memory. Harari notes that they expect to commercialize an improved multilevel cell product in 2008 that meets solid state computer drive requirements. He says his company has started supplying solid state drives to IBM Corp. and Dell Inc., and Intel Corp has decided to use them for low cost personal computers.

Toshiba plans to keep using its floating gate structure through the 30nm generation, now targeted for sample shipments in the second half of 2009 and volume production in early 2010. But the company will need to develop another new set of materials, probably a fully silicided metal electrode for the control gate, as well as a better high-k inter-poly dielectric. And Toshiba expects to use double patterning immersion as the only practical way to get 30nm features at that date.

Toshiba Semiconductor president Shozo Saito says 2009-2010 is also its target for introducing 4 bits/cell storage technology. The company has demonstrated a 16Gbit chip using 4 bits/cell with a 70nm design rule; the 168mm2 chip is only about 15% bigger than a 2 bit/cell version. With 16 different closely spaced voltage levels to distinguish, though, writing speed remains slow (<1Mbyte/sec). SanDisk's chairman Harari notes the prototype using controller technology from its Israeli acquisition, msystems Ltd., underperformed the 2 bit/cell product, so considerable development work remains.

At the 20nm generation, even Toshiba will have to give up its floating gate for a new cell structure. Hiroshi Nakai, head of flash memory strategy, says the company will likely turn to a SiN charge trap cell, aiming for production in 2011-2012 — likely with 13.6nm EUV lithography, which Nakai says now seems likely to be available by 2011. At 10nm, another new and probably 3D structure will likely be required, based on charge trap or cross-point junctions.

“I think it will be difficult to make floating-gate cells beyond 22nm, so we’re developing 3D structures, using the one-time-programmable 3D memory know-how we acquired with our purchase of Matrix Semiconductor,” says SanDisk chairman Harari. “We’re concentrating on cross point cells like Matrix’s that don’t use transistors — though for NAND flash, we need to develop a material that can be re-written, not just programmed once like Matrix’s.” — P.D.

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