Pixelated phase-shift computational techniques developed for sub-wavelength 4X maskmaking

by Bob Haavind, Editorial Director, Solid State Technology

Problems with complex circuit patterns using alternating phase shift masks for low k1 lithography, even with strong off-axis illumination, led Intel to experiment with using pixels — about a trillion of them for a 65nm mask layer — for imaging. A number of papers at this year’s SPIE Advanced Lithography Conference described the techniques developed to successfully do the critical first metallization layer (M1) using pixelated phase-shift masks.

The trouble with phase shift came when exposure wavelengths became smaller even than the features on a 4× mask, according to Intel’s Y.A. Borodovsky, et. al. Undesirable “thick mask” effects results from interactions between the light radiation and mask materials and features. Pixelated Phase Mask (PPM) technology, using pixels with lateral dimensions much smaller than the wavelength, was developed as an alternative.

Investigations showed that while an alternating phase shift approach with highly coherent illumination proved robust for simple patterns, more complex structures were better handled by a phase-edge style with off-axis illumination, according to R.E. Schenker of Intel in a companion paper. Thus, to avoid design restrictions, the off-axis approach was chosen. Also, while a three-tone pixel mask (unetched glass, etched glass and chrome) offered superior patterning capabilities, a two-tone chromeless mask gave better CD control by avoiding CD shifts due to variations in e-beam alignment.

The size of individual pixels did not have much effect on final patterning performance, but MEEF effects were very asymmetric — so CD displacement in one direction would have little effect, but patterning would be degraded if it was in the other direction. This required the use of rule-based compensation, and wafer data was used to derive required mask making tolerances for pixel masks, including phase and glass angle uniformity.

The techniques were applied for the M1 layer of a 65nm microprocessor, and mask defects were successfully detected and repaired, according to Schenker. Early versions of full-chip pixel designs had some areas with weak images, but those weak patterning sites were corrected. Schenker concluded that there will be some issues in scaling this pixilation technology, and new mask materials may be needed to deal with them.

Getting pixilation to work required some heavy duty modeling, as described by Vivek Singh, et. al. of Intel in a paper quaintly titled “Making a trillion pixels dance.”

A thin mask model proved entirely inadequate, and although a thick mask model was better, it still needed considerable tuning. A rigorous model based on an optimization algorithm would be best, but the number of possible combinations of a trillion pixels on the final product mask would prove larger than the number of elementary particles in the known universe, Singh lamented. Once an upgraded thick mask model was devised, the software had to be extended from the μm to cm length scale for full-chip layout, with several non-trivial components such as handling pixilated domain boundaries, repair of regions where image quality did not converge, and then verification of the entire assembled database.

Although the exercise taught Intel a good deal, the approach evidently has been abandoned. — B.H.

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