by M. David Levenson, Editor-in-Chief, Microlithography World
(Fourth in a four-part series)
Avoiding unprintable structures will be essential for manufacturing 45nm and smaller circuits, and that was reflected in a series of papers on design for manufacturing and design rule restrictions, some of them quite aggressive.
Avoiding unprintable structures will be essential for manufacturing 45nm and smaller circuits, and that was reflected in a series of papers on design for manufacturing and design rule restrictions, some of them quite aggressive. Keynote speaker Andrew Kahng of UC San Diego introduced the idea of “design for equipment” (DfE), where designers learn to accommodate specific patterning and metrology capabilities. The most dramatic example was presented by a collaboration of NXP semiconductors and ASML which found a way to make 45nm logic cells using a 0.93NA 248nm scanner. They key was a very constrained grating like layout. However, the area of the cells increased ~15% compared to a more typical layout for high-NA immersion production.
The idea of a 1D grating-like design was taken to an extreme, perhaps, by Mike Smayling and Tela Innovations, who showed how libraries of standard cells could be converted to 1D layouts and snapped together. Simulations using the Brion Tachyon system revealed much improved process latitude, and many Tela designs were actually smaller than their 2D predecessors.
In his keynote for the DfM sessions, Lars Liebmann of IBM foretold an era of “hard DfM” where all challenges would have to be addressed through computation. That differed from the recently past time of “soft DfM” where marginal improvements were occasionally made by optimizing geometries, but much more of the progress resulted from improved tooling. That time is over. From now on, according to Liebmann, all tradeoffs will have to be integrated into one seamless design and process flow. To begin getting the industry to speak the same language, Liebmann announced a project within the Silicon Integration Initiative to capture and regularize DfM terminology and mentioned nine other DfM related programs at Rensselaer Polytechnic Institute.
The increased apparent importance of computational lithography launched something of an arms race among OPC and EDA companies. It began, as these things do, with Brion/ASML announcing an improved Tachyon monolith for faster OPC optimization. Gauda, a stealth start-up, decloaked to tout its method of cheap commodity graphical processor units for OPC, for only $300,000. Mercury Computer Systems announced that its cell-processor based blade accelerator (CPA) had been qualified to run Mentor Graphics’ nmOPC for 45nm production at IBM. Previously, IBM had been using BlueGene for heavy-duty litho simulation. The smallest Mercury 25U dual cell-based blade system (with 14 blades) runs at 1 teraflop for $250,000, according to Jim McKibbin of Mercury. On a network, it looks like just another node. Since the Cell can be reprogrammed using software (unlike an FPGA) and is intrinsically parallel (unlike x86’s), Mentor and Mercury believe the system is more flexible than other commercial computational lithography hardware.
No one outside Intel knows what it is using for its production and pixelated mask designs, and rumors of even faster kludges could be heard in the hallways. So, while there is no new wavelength or exposure tool, there seem likely to be new litho computers and applications. — M.D.L.
Click here for all the separate analyses from this package of SPIE writeups: a list of what’s still needed to enable 32nm generation chips printed with double patterning technology; problems, yet promise, in development of EUV; litho projects (e.g. phase-shift and high-index immersion) that are falling behind the curve, and others that need a boost (e.g. imprint); and clever new technologies added to the equation, and what’s sparked an “arms race” among OPC and EDA firms.