Flip Chip’s Midlife Crisis

BY GEORGE A. RILEY, Contributing Editor

Flip chip assembly, a 45-year-old technology, is undergoing a midlife crisis. The greedy market demands higher density, smaller size, higher performance, and lower cost. However, as feature size shrinks to create higher density, flip chip bump size and pitch also shrink, as does the gap under the die, where flux residues hide and underfills creep in. Higher performance generally means faster circuits, consuming more power. More power in a smaller space raises temperatures, requiring better heat transfer to avoid hot spots that threaten both performance and reliability.

All of these normal technical problems are compounded by the political edict mandating lead-free electronics. This decision was evidently based upon faith rather than science, without consideration of the consequences. Now the industry must meet the market requirements while burdened with artificial limitations that lead to higher process temperatures, higher costs, potentially lower device reliability, and significant environmental hazards.

Figure 1. PiP cross section shows flip chip bumps above solder balls. (Courtesy of STATSChipPAC)
Click here to enlarge image

Some struggle to find new solutions to this dilemma. Others strive to improve available substitutes for lead-free alloys. One consequence is the dramatic change forecasted in the market mix of bumping technologies. According to Prismark Partner’s Semiconductor & Packaging Report, electroplated solder and electroplated gold bumped wafers will drop from 70 to 44% of total production within 5 years, while transfer-bumped and copper-bumped wafers are expected to grow from 22 to 46%. Table 1 shows total bumped wafer production for 2006 and 2011 expressed as millions of equivalent 200-mm wafers, and the compound annual growth rate (CAGR) of each bumping technology over the period.

Electroplated solder has been the “gold standard” for many years; a frequent choice for high-quality fine-pitch bumps. Unfortunately, first-generation lead-free solders favor three-element combinations of the ubiquitous tin-silver-copper (SAC) alloys — far more difficult to electroplate than time-proven eutectic lead-tin. Worse, second-generation lead-free solders now in development may result in four-element alloys, which are even more difficult to electroplate. Hence, the forecasted decline in electroplated solder share. Electroplated gold drops share for the pedestrian reason that it primarily serves display drivers, and shares their projected slower growth rate across this period.

“Transfer bumping” during this period primarily consists of injection-molded solder and “ball drop” of pre-formed solder spheres. Injection molding molds the bumps from a reservoir of molten metal of any meltable composition, including SAC. Spheres, like solder paste, may be easily formed for SAC or other multi-metal solders.

Table 1. Total flip chip bumped wafer production in millions of 200-mm wafer equivalents per year. (Prismark Semiconductor & Packaging Report)
Click here to enlarge image

Copper bumping thrives by being both lead-free and by offering improvements in electrical and thermal conductivity, strength, compatibility with board and wafer metallurgy, and tighter spacing. Slender copper pillar bumps with solder caps allow closer pitch than pudgy little spheres of solder, without squeezing the underchip gap.

The “other” category of solder paste, stud bumps, electroless plated nickel, and conductive adhesives gains share for a pair of opposed reasons. Paste, a common approach for low-cost consumer products, easily adapts to lead-free solders. Conversely, stud bumps, electroless nickel, and conductive adhesive avoid lead-free solders, offering low process temperature lead-free bumping.

Converting manufacturing to lead-free solders has already cost the industry an estimated $20 billion. Unfortunately, that cost is still growing, although more slowly than expected. More than 50% of solder pastes sold in the U.S. and in Western Europe are still leaded. This may reflect the continued exclusion of lead-free solders from high-reliability applications. While SAC305 currently reigns as the popular solder-paste alloy, a growing interest in lower silver content alloys is driven by the rising cost of silver.

Contract wafer bumpers such as TLMI, offering a variety of bump materials and processes, continue to see a mixed business. They find that the demand for copper and lead-free bumps is growing steadily, but not as rapidly as expected, and not at the expense of a still-healthy lead solder demand.

The following samples of recent technical developments show industry progress in meeting the market, thermal, and regulatory needs.

Meeting Market Needs

the former SUSS bonder division, introduced the FC300 bonder, offering up to 4,000-newton bonding pressure with unsurpassed planarity for 300-mm wafers. The FC300 bonds 100-mm by 100-mm devices by thermocompression or several other means, allowing flip chip die stacking of larger, more complex high-bump-count devices onto wafers.

STATS ChipPAC introduced package-in-package (PiP) flip chip assembly in a 3D stack for high-end cellular handsets. A packaged memory chip is encapsulated along with two other thinned bare digital signal and analog die into a 1.35-mm thick PiP module. Unique technology is required to thin and handle bumped wafers with the wafer thickness of 100 μm, approximating the height of the bumps themselves. Figure 1 shows a package cross-section. The flip chip bumps are the tiny white dots above the package solder balls.

IBM demonstrated injection-molded C4NP microbumps at 50-μm pitch for higher density packaging. Results show that this is not the minimum attainable pitch for this process. Microbump flip chip assembly is replacing wire bonding in some stacked-die packaging.

Fraunhofer IZM demonstrated AuSn solder bump suitability for very high frequency connections. A 100 GHz photodetector suitable for high-frequency data systems was connected to thin-film microstripline through 50-μm diameter plated AuSn bumps. The fluxless Au/Sn assembly process avoids contaminating optical surfaces. Gold stud bumps with thermocompression or thermosonic bonding were also found suitable for similar lower-temperature connections.

B-Tech introduced a low-pressure anisotropic conductive adhesive (ACF) for flip chip assembly. The adhesive is filled with closely spaced, carefully oriented insulation-clad nickel wires in the adhesive matrix. The wires allow bump pitches to 11 μm, compared with 75 μm for conventional AFC. Bonding pressure is below 50 psi, compared to the usual 300 psi, and material costs are much lower.

Surfect introduced a single-chamber multi-metal plating system with high plating rates. It produces high quality multi-metal bumps with significantly lower equipment cost than conventional multi-tank equipment. Small, individual, single-chamber systems can replace multiple large tanks of hazardous plating chemicals.

Solving Heat Problems

The thermal problem resulting from more power in smaller volumes has stimulated some bump-related solutions.

Nextreme announced integrating thin film thermo-electric coolers (eTEC) into copper pillar flip chip bumps. This combination could eliminate die “hot spots” which often limit IC cooling. An advantage is that each cooler is bump-size, controlling the hot spots on a single die, rather than trying to cool the whole die.

Fujitsu Labs continues development of their pioneering carbon nanotube bumps. This alternative approach to device cooling for high-power transistors depends upon the very high thermal conductivity of carbon nanotubes, which is many times that of gold. The nanotube bumps originate at the hot spots on the die, shortening the thermal path.

Figure 2. Solder transfer tool for C4NP processes. (Courtesy of Tom Way for SUSS Microtec)
Click here to enlarge image

Delphi Electronics has detailed the high-temperature advantages of eutectic tin-lead bumps doped with up to 3% copper. Flip chip assembly to ceramic or laminates showed improved high temperature operating life and better high-temperature electrical conductivity.

Spectra-Mat introduced a line of thermal-expansion-matched substrates and covers for wafer-level packaging of MEMS and optical devices. The substrates are tungsten-copper and molybdenum-copper composites, with a selectable range of expansion coefficients determined by the relative proportions of materials in the composite. They are ideal for high power devices adversely affected by thermal gradients.

Solving Lead-free Problems

An estimated 8,300 new reflow ovens were purchased in 2006, largely in response to the higher-temperature, longer ramp times, and closer control required for lead-free solder reflow.

Lead-free alloy reliability is still a serious concern in high-reliability, long-lifespan applications such as military, aerospace, and medical. Conference papers report continuing progress on unresolved lead-free solder problems. For example, one recent conference included papers by Samsung on tin whisker growth, by Freescale Semiconductor on lead-free solder electromigration, and by Arakawa Chemical on lead-free flux cleaning problems.

Research continues on improved next-generation lead-free solders. A recent paper by lead-free solder manufacturer Indium Corporation identifies 8 areas where current lead-free solders must improve to meet the needs of expected further miniaturization. These include lower melting temperatures, better solder spreading, and higher resistance to electrochemical migration.

Amkor’s lead-free process development shows that present manufacturing equipment and processes can produce satisfactory 150-μm pitch lead-free solder bumps on low-


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>



Astronics Test Systems announces new PXIe test instruments
01/24/2017Astronics Corporation, through its wholly-owned subsidiary Astronics Test Systems, introduced two new test instruments today. ...
Edwards launches new Smart Thermal Management System at SEMICON Europa 2016
10/25/2016Smart TMS helps semiconductor, flat panel display and solar manufacturers improve their process performance and safety by red...
Tektronix introduces Keithley S540 power semiconductor test system
10/19/2016Tektronix, Inc., a worldwide provider of measurement solutions, today introduced the Keithley S540 Power Semiconductor Test System, a ...