3D for microprocessors now…TSV later

by Ed Korczynski, senior technical editor, Solid State Technology

May 21, 2008 – While manufacturing of 3D ICs is today limited mostly to memory chip stacks and cell-phone camera modules, the next huge application seems to be the embedded memory in microprocessors. Subramanian Iyer, distinguished engineer and chief technologist of IBM’s Systems and Technology Group, explained the economic considerations behind 3D microprocessors at the ConFab 2008 in Las Vegas, Nevada.

The economics of any new technology need to be assessed with respect to the advantages of other competing approaches that provide the same or similar benefits. Both embedded DRAM in a system-on-chip (SoC) and stand-alone DRAM as part of a system-in-package (SiP) have been well established as 2D solutions, so any 3D approach must be compared to these proven techniques. Iyer made his case by examining the relatively straightforward but very important challenge of balancing memory with 64 processor cores in a system.

It is certain that 3D integration promises improved functionality in reduced physical volume when compared to the same circuitry running only in 2D. However, optimizing circuitry for 3D through re-design offers the potential for even greater benefits such as system-level co-design and the use of different fab technologies to create the different IC levels. For example, memory and logic manufacturing can be independently optimized on different production lines to reduce overall system cost.

In today’s microprocessor SoC, the first consideration in embedded memory is whether to choose IT-IC DRAM or 6T SRAM. Compared to DRAM, SRAM is about twice as fast and ~3.5× less dense in Mb/mm2. Since SRAM is built using only transistors, it can be integrated with no additional processing steps over those needed for logic. DRAM, however, needs the charge-storage capacitor and associated unique masks and processing steps, such that embedding it with logic adds to the cost of node manufacturing.

The result of all of the modeling is the conclusion that if much of the die area is eSRAM, then it will be cost-effective to replace it with eDRAM. There has been a general trend in modern microprocessor layouts that the percentage of silicon area devoted to memory has increased as the circuitry has shrunk. As a result, eDRAM has become ever more attractive, and new technology solutions such as 3D must be explores.

For multicore cache-starved microprocessors, the case for 3D integration is very favorable. There is no known alternative which could provide similar functionality, and TSV manufacturing technology has made significant advances recently. However, lack of design tools and clear directions for thermal/power management remain as stumbling blocks. It also seems certain that significantly increased functionality will have to be shown, since cost/area of silicon will probably have to increase for the use of TSV.

The motivation to develop 3D IC manufacturing technology is strong across the industry today, in part due to the challenges of pushing 2D IC integration to ever smaller dimensions. Traditional 2D scaling now must contend with the costs involved in pushing optical lithography below 1/4 wavelength as well as the inherent challenges of controlling atomic-scale films. 3D has a place in the future, but Iyer reminds us that — like any engineering problem — there are inherent tradeoffs, and each unique application needs to be considered independently to arrive at the optimal solution. — E.K.

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