May 29, 2008 – Intel and Micron’s announcement that their JV IM Flash Technologies has developed a 34nm NAND flash device could have two significant impacts on the market: give the companies a better cost/profit profile vs. competitors, and/or help stretch an already painful oversupply situation well into the next year, according to a report from Objective Analysis.
The companies note that they started making NAND flash with 72nm process technologies in 2006, well behind others’ pace, but now claim to have caught up and even have a six-month lead. They skipped the 4x node entirely, jumping from 52nm to 34nm, to produce a 172sq. mm (4GB) MLC NAND chip that can fit in a standard TSOP package, with samples currently shipping.
The announcement can be taken one of two ways, noted Objective Analysis analyst Jim Handy, in a research report. As NAND flash oversupplies and prices stay low, one way for memory firms to keep afloat is to find ways to lower their costs. A 172sq. mm die size on 300mm wafers should yield about 400 diced chips/wafer, with a price of 32Gb chip roughly $4/chip, or about $0.99/GB — “the first to break the $1.00/GB barrier,” he notes. Today’s MLC NAND prices are “hovering near $2.50/GB,” roughly equivalent to a 54nm/300mm MLC chip or 45nm/200mm chip, and most NAND makers are expected to shift to 45nm/300mm this year to lower their costs to about $1.75/GB. “With a $0.99/GB price, the new IMFT chip can be expected to reap impressive margins as long as NAND prices stay above their competitors’ costs,” Handy writes. They will “either profit during these difficult times, or at least to suffer smaller losses than will other suppliers,” and carve out a larger share of the market.
On the other hand, jumping to an even finer process node could cause a NAND market oversupply situation to linger longer than expected. SanDisk has weighed in with projections that an oversupply will last through 2008 and into 1H09, as does the analyst firm; “other NAND companies are likely to follow suit,” Handy writes. A shift to 34nm devices, starting with IMFT, “might cause an oversupply to last an additional quarter,” he notes.
In another analysts’ take on the announcement, Gartner’s Joseph Unsworth agrees that development of a 34nm NAND device goes a long way to drive down costs, noting that IM Flash did it without the need for an onboard NAND controller, and using immersion litho. “Controller technology will be essential to adoption, with ECC likely to be at least 12 bits per 512-byte block, and Intel and Micron have been separately developing their own controller solutions, as well as cooperating with external controller companies to expedite adoption,” he wrote, in a research note.
While IM Flash can wave the banner for NAND process node leadership (at least temporarily), Unsworth points out that another cost-reducer is multistate technology, e.g. 3- and 4bit/cell technology. Toshiba/SanDisk used MLC technology (2002-2005) to keep up with Samsung in terms of cost, despite Samsung’s process geometry lead, he notes, and the two aim for 50% bit output based on 3bit/cell technology that ” will evolve as a necessary technology for commodity NAND flash,” he says. IM Flash is still looking at this technology as an option, but further development will be needed to keep pace with others in the industry.
Yet another concern for IM Flash is its fab capacity. The firm’s Singapore fab is scheduled to ramp up in early 2009, with anticipated 65,000 wafer/month capability — well behind planned expansions in 2010-2011 by others in the industry, Unsworth notes. A decision about future capacity plans “must be made soon regarding the status of new capacity for the 2010 and 2011 time frame if it is going to exploit the advantages gained from this announcement,” he writes. Intel and Micron have seen their NAND profits suffer during a tough NAND market period (2006-2008), “and additional spending will test the resolve of both companies, especially Intel’s long-term commitment, which has been under attack.”