Economics may drive push to 3D ICs, says SEMATECH’s Arkalgud

by Bob Haavind, Editorial Director, Solid State Technology

May 21, 2008 – Beyond today’s stacked chips in a package may come higher performance 3D stacked ICs using through-silicon vias (TSV) to interconnect layers, according to Sitaram Arkalgud, who spoke on the economic implications of 3D at ConFab 2008 in Las Vegas.

Stacking chips within a package lowers footprint and raises density, and can boost yield by optimizing wafer processing for memory, logic, and other types of stacked chips. Improved integration of heterogeneous technologies and materials, as compared to the system-on-a-chip (SoC) approach, can also be achieved in 3D stacks, offering higher functionality, according to Arkalgud. Shorter wiring will mean higher bandwidth, boosting performance. Shorter wires will also lower power requirements and reduce overall I/O count, he added.

There also are potential cost advantages for 3D, Arkalgud explained. If there is any slowdown in scaling, 3D can provide an alternate path to productivity gains. The cost structure can be optimized for each “level” in the stack, he said, and time to market can be shorter by combining specialized chips in one package.

If the technology for TSVs can be developed and made cost-effective, it can offer all of these advantages, he pointed out.

SEMATECH expects that there will be a progression of 3D product needs and applications, according to Arkalgud. Right now 3D is offering improvements in density and form factor for memory (such as flash and DRAM) and for CMOS image sensors. Other applications involving performance and functionality improvements might follow, with microprocessors stacked with SRAM cache chips by about 2010, and higher complexity combinations of logic and various types of memory after 2012. Perhaps sometimes after 2012, Arkalgud suggested, 3D with TSV might go beyond just CMOS, with CMOS “levels” maybe stacked with other specialized devices such as MEMS, optoelectronics, biosensors, and others.

Industrywide collaboration will be needed to achieve the higher levels of complexity, Arkalgud pointed out, so that it will take some time to reach these capabilities. TSV technology can deliver the highest performance and functionality, and minimize costs, he said.

While shrinks have driven density and performance for many chip generations, there is a steadily rising cost of ownership (CoO) to achieve them. Lithography for future generations will require immersion with double exposure and double patterning, and eventually EUV, to maintain the shrink roadmap. Transistors will require high-k dielectrics, metal gates, and perhaps 3D structures, such as FinFETs. Metallization will require complex low-k dielectric integration.

High density could alternatively be achieved with the use of 3D stacking, while delaying introduction of the complex technologies needed to continue the traditional shrink. This can be achieved without an area-driven yield penalty, he pointed out, by stacking smaller die instead of using a single, large 2D die. Shorter connections using through-silicon and through-substrate vias can also reduce interconnect delays. The TSV approach can contain rising COO by extending technology life cycles, he said.

One possibility for TSVs is wafer-to-wafer integration, processing hundreds of stacked die in parallel, which could reduce costs considerably, according to Arkalgud. But there are severe constraints to this approach. Both wafers and the die on them will have to match in size, and heterogeneous integration would require a rethinking of design. Yield would have to be very high, and technologies would be restricted.

In the near term, die-to-wafer integration has a better cost structure, Arkalgud said. Favorable stack yields can be obtained by using known good die (KGD). Mix and match capabilities could offer very quick time to market potential, he added. Yield will be a critical factor, and must be included in any cost modeling.

Die to wafer 3D integration would permit different wafer and die sizes, and non-leading-edge chips from depreciated factories could be combined with the latest devices to achieve high performance/high functionality stacks. He contrasted this to the SoC approach, which requires the same technology node for all elements. But for this approach to develop, the industry will have to devise chip-to-chip connection standards and roadmaps, he explained.

Arkalgud concluded that 3D could serve as an engine to keep the industry on its long-term productivity curve, achieving high performance and functionality. Many technology elements are involved, allowing productivity benefits at many levels, he said — but comprehensive cost models will be essential to quantify these benefits, and the needed capabilities will only be achieved through industry-wide collaboration. — B.H.

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