BY LEE SMITH, Amkor Technology
Leadframe-based packages accounted for over 70% of the 147 billion IC packages produced in 2007. The quad flat no lead (QFN) and quad flat pack (QFP) are two of the fastest growing leadframe package families. As proof that there are still opportunities to innovate in this sector, a novel leadframe-based technology* was developed; incorporating QFN and QFP technologies by integrating inner lands within a standard exposed pad QFP package outline.
Managing silicon performance increases in a low cost package platform were the key development challenges. The solution fuses QFN and QFP technologies to extend pin-count capability or increase I/O density of leadframe packaging. The resulting platform provides double the I/O within a current QFP footprint, or 50% reduction in body size for an existing lead count. However, the electrical and thermal performance it offers enables designers to design devices into a low-cost leadframe platform that can meet the size and performance requirements that historically would have to be addressed by a custom PBGA package. This technology’s design flexibility in signal, power, and ground-pin optimization, coupled with the thermal benefits of exposed-pad technology enable the package to serve high speed or RF applications up to 10 gigabits/second, or 10 GHz, and dissipate over 4 watts of power.
Isometric and cross section views of a complete leadframe-based package.
System-level and IC designers require a range of features to support higher I/O, power, and ground-pin-count densities. These package design challenges increase as designers take advantage of the higher integration available in 65- and 45-nm CMOS. As such, this platform’s design features include lead counts approaching 400 pins with roadmap to higher pin counts, a 10